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i.MX fixes for 6.0, 2nd round:
- A couple of TQMa8MPQL device tree fixes from Alexander Stein on button GPIOs and PCF85063 RTC alarm pinctrl. - Include phy-imx8-pcie.h header in tqma8mqml-mba8mx device tree to fix build errors when this SoM dtsi is included on customer carrier boards. - Remove GPU power domain reset from i.MX8MN device tree to fix a sporadical hang seen with GPUMIX powering up. - Correct CPLD_Dn GPIO label mapping for Toradex Verdin based Menlo board. - Add ARCH_NXP back to defconfig, which was dropped accidentally by commit566e373fe0("arm64: Kconfig.platforms: Group NXP platforms together"). - Add missing #reset-cells for i.MX8ULP PCC clock controllers. - Update PMIC voltages for imx8mm-verdin board to fix an issue with one Toradex SKU that uses a consumer-grade chip that is capable of going up to 1.8GHz at 1.00V. - A series of imx8mp-venice-gw74xx device tree changes from Tim Harvey to fix things on CAN STBY polarity, KSZ9477 CPU uplink port and phy-mode. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmMhTsEUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM64hwf/eBQJ7ZE/HKw4UavMZWmoGMhAnqXs MbN2rWl68C/j+Sl05h86MZR7/Ejmjo0x0db0mosMrcDWoufZM6zSSFjU9ncviSYT z4q5lgXdE2BSvSWoVfML4j9M+kU0+VWPFbRCynkGifV7Km/sTfVgbfKZaxo+UqYO 9mV6iZP9wCn4/+4vA01WOUfl294icqizN0iDEiWpHI8EobsdeGlYXgclfd6twJO7 Io/ooPppaJxM+3ZiY0+ZGfkX0fJOncRjSvA5SALys2h0OsHlyu43AcG2CEGP8/fl GhweRmIKXqlwWwJxkKf8vp37L4Ao5Syl5IBaY+FqyVYtbz9GGdvUbrA/XQ== =E1d7 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMjNDgACgkQmmx57+YA GNmjcxAAoI1siIoOI0dFgru6i64QGfASE4RQZGWFVyAFu4kTG7jblrHFi3ejNx2J UP+4YoiUSaml7d933cs4Rp5AKe3H87NN/451pLvQ0hFic+GBNOduIHaKcMPxImM0 HSszajoXmTBDgb6a5Cmh0CS1tfmhKCvyO8ubFC1slC24+9dJ/AdyJzH0sQf6iB4W YluDXjWr5PaLa30ZCqgOHsXjZc3fWXUauHAKoQXL8stve7uG/r3pHPy7lJATN5CM hUBvKGOSp3sJYau+n5+IUcwrBAjpDm7CNcpLFued7iZypTO0/LJpLRlo925YV2Kb fZOkz3rmF4EwXZBSyKeEpa+U2XVj7/PgOLaObIIf7O64QYoStmjaEHauv85VWLvJ T5MzmrU+tgds1Jk2VhmJSKj6ctFLt87xt0ZKUF3BUb+PgBLubavrI0NME7RIiN02 deFPnyEF0YThXRp6jwYO7auFgnF/xUmlJy76+fB7S6O2bXybZAQga4ng8KNkuCo6 JX0c5UOKrfYjVxBZ0GjFQG6k9zhXTsMFzFU0MKynVB9PSQnRadPmAWMU7wXN2dXW aVjzLntVUblybjyZFHykXRgBhlRMB72qvdIGZXimkxuE+F/v+khSbQY9PxQfg2dY uwLOQ5HQijz9/lSE+315KBy9REOLUyqvT7QRfeEj4AzGGPtHAw4= =OdRx -----END PGP SIGNATURE----- Merge tag 'imx-fixes-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 6.0, 2nd round: - A couple of TQMa8MPQL device tree fixes from Alexander Stein on button GPIOs and PCF85063 RTC alarm pinctrl. - Include phy-imx8-pcie.h header in tqma8mqml-mba8mx device tree to fix build errors when this SoM dtsi is included on customer carrier boards. - Remove GPU power domain reset from i.MX8MN device tree to fix a sporadical hang seen with GPUMIX powering up. - Correct CPLD_Dn GPIO label mapping for Toradex Verdin based Menlo board. - Add ARCH_NXP back to defconfig, which was dropped accidentally by commit566e373fe0("arm64: Kconfig.platforms: Group NXP platforms together"). - Add missing #reset-cells for i.MX8ULP PCC clock controllers. - Update PMIC voltages for imx8mm-verdin board to fix an issue with one Toradex SKU that uses a consumer-grade chip that is capable of going up to 1.8GHz at 1.00V. - A series of imx8mp-venice-gw74xx device tree changes from Tim Harvey to fix things on CAN STBY polarity, KSZ9477 CPU uplink port and phy-mode. * tag 'imx-fixes-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8mp-venice-gw74xx: fix port/phy validation arm64: dts: imx8mp-venice-gw74xx: fix ksz9477 cpu port arm64: dts: imx8mp-venice-gw74xx: fix CAN STBY polarity arm64: dts: tqma8mqml: Include phy-imx8-pcie.h header arm64: defconfig: enable ARCH_NXP arm64: dts: imx8mp-tqma8mpql-mba8mpxl: add missing pinctrl for RTC alarm arm64: dts: imx8mm-verdin: extend pmic voltages arm64: dts: imx8ulp: add #reset-cells for pcc arm64: dts: tqma8mpxl-ba8mpxl: Fix button GPIOs arm64: dts: imx8mn: remove GPU power domain reset arm64: dts: imx8mm: Reverse CPLD_Dn GPIO label mapping on MX8Menlo Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
7b9a516a91
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@ -152,11 +152,11 @@ &gpio4 {
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* CPLD_reset is RESET_SOFT in schematic
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*/
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gpio-line-names =
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"CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
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"", "CPLD_D[0]", "", "",
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"", "", "", "CPLD_D[2]",
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"CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
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"CPLD_D[7]", "", "", "",
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"CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
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"", "CPLD_D[7]", "", "",
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"", "", "", "CPLD_D[5]",
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"CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
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"CPLD_D[0]", "", "", "",
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"", "", "", "",
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"", "", "", "KBD_intK",
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"", "", "", "";
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@ -5,7 +5,6 @@
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/dts-v1/;
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mm-tqma8mqml.dtsi"
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#include "mba8mx.dtsi"
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@ -3,6 +3,7 @@
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* Copyright 2020-2021 TQ-Systems GmbH
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*/
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mm.dtsi"
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/ {
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@ -367,8 +367,8 @@ reg_vdd_arm: BUCK2 {
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nxp,dvs-standby-voltage = <850000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <950000>;
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1050000>;
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regulator-min-microvolt = <805000>;
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regulator-name = "On-module +VDD_ARM (BUCK2)";
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regulator-ramp-delay = <3125>;
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};
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@ -376,8 +376,8 @@ reg_vdd_arm: BUCK2 {
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reg_vdd_dram: BUCK3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <950000>;
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1000000>;
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regulator-min-microvolt = <805000>;
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regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
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};
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@ -416,7 +416,7 @@ reg_nvcc_snvs: LDO1 {
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reg_vdd_snvs: LDO2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <900000>;
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regulator-max-microvolt = <800000>;
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regulator-min-microvolt = <800000>;
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regulator-name = "On-module +V0.8_SNVS (LDO2)";
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};
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@ -672,7 +672,6 @@ pgc_gpumix: power-domain@2 {
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<&clk IMX8MN_CLK_GPU_SHADER>,
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<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
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<&clk IMX8MN_CLK_GPU_AHB>;
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resets = <&src IMX8MQ_RESET_GPU_RESET>;
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};
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pgc_dispmix: power-domain@3 {
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@ -57,13 +57,13 @@ gpio-keys {
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switch-1 {
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label = "S12";
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linux,code = <BTN_0>;
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gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
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gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
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};
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switch-2 {
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label = "S13";
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linux,code = <BTN_1>;
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gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
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gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
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};
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};
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@ -394,6 +394,8 @@ &i2c6 {
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&pcf85063 {
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/* RTC_EVENT# is connected on MBa8MPxL */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcf85063>;
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interrupt-parent = <&gpio4>;
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interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
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};
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@ -630,6 +632,10 @@ pinctrl_lvdsdisplay: lvdsdisplaygrp {
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fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */
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};
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pinctrl_pcf85063: pcf85063grp {
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fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>;
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};
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/* LVDS Backlight */
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pinctrl_pwm2: pwm2grp {
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fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>;
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@ -123,8 +123,7 @@ reg_can2_stby: regulator-can2-stby {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_can>;
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regulator-name = "can2_stby";
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gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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@ -484,35 +483,40 @@ ports {
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lan1: port@0 {
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reg = <0>;
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label = "lan1";
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phy-mode = "internal";
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local-mac-address = [00 00 00 00 00 00];
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};
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lan2: port@1 {
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reg = <1>;
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label = "lan2";
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phy-mode = "internal";
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local-mac-address = [00 00 00 00 00 00];
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};
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lan3: port@2 {
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reg = <2>;
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label = "lan3";
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phy-mode = "internal";
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local-mac-address = [00 00 00 00 00 00];
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};
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lan4: port@3 {
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reg = <3>;
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label = "lan4";
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phy-mode = "internal";
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local-mac-address = [00 00 00 00 00 00];
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};
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lan5: port@4 {
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reg = <4>;
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label = "lan5";
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phy-mode = "internal";
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local-mac-address = [00 00 00 00 00 00];
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};
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port@6 {
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reg = <6>;
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port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <&fec>;
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phy-mode = "rgmii-id";
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@ -172,6 +172,7 @@ pcc3: clock-controller@292d0000 {
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compatible = "fsl,imx8ulp-pcc3";
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reg = <0x292d0000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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tpm5: tpm@29340000 {
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@ -270,6 +271,7 @@ pcc4: clock-controller@29800000 {
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compatible = "fsl,imx8ulp-pcc4";
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reg = <0x29800000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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lpi2c6: i2c@29840000 {
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@ -414,6 +416,7 @@ pcc5: clock-controller@2da70000 {
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compatible = "fsl,imx8ulp-pcc5";
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reg = <0x2da70000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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@ -48,6 +48,7 @@ CONFIG_ARCH_KEEMBAY=y
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CONFIG_ARCH_MEDIATEK=y
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CONFIG_ARCH_MESON=y
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CONFIG_ARCH_MVEBU=y
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CONFIG_ARCH_NXP=y
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CONFIG_ARCH_MXC=y
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CONFIG_ARCH_NPCM=y
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CONFIG_ARCH_QCOM=y
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