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Merge branch 'arm/fixes' into soc/late2

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* arm/fixes:
  arm64: dts: imx8mm-tqma8mqml: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mn-tqma8mqnl: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mm-emtop-som: Correct PAD settings for PMIC_nINT
  reset: amlogic: t7: Fix null reset ops
  arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-ultra-mach-sbc: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-sr-som: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-nitrogen-som: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-aristainetos3a-som-v1: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-edm-g: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-icore-mx8mp: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-navqp: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-debix-som-a: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-debix-model-a: Correct PAD settings for PMIC_nINT
  dt-bindings: arm64: add Marvell 7k COMe boards
This commit is contained in:
Arnd Bergmann 2026-04-20 17:02:56 +02:00
commit 7b82df3368
17 changed files with 30 additions and 18 deletions
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11
Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
View File

@ -21,6 +21,17 @@ properties:
- const: marvell,armada-ap806-dual
- const: marvell,armada-ap806
- description:
Falcon (DB-98CX85x0) Development board COM Express Carrier plus
Armada 7020 SoC COM Express CPU module
items:
- const: marvell,armada7020-falcon-carrier
- const: marvell,db-falcon-carrier
- const: marvell,armada7020-cpu-module
- const: marvell,armada7020
- const: marvell,armada-ap806-dual
- const: marvell,armada-ap806
- description: Armada 7040 SoC
items:
- enum:

4
arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi
View File

@ -60,7 +60,7 @@ pmic@25 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
@ -194,7 +194,7 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
pinctrl_pmic: emtop-pmic-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
>;
};

2
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
View File

@ -292,7 +292,7 @@ pinctrl_i2c1_gpio: i2c1gpiogrp {
};
pinctrl_pmic: pmicgrp {
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>;
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1d4>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {

2
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi
View File

@ -283,7 +283,7 @@ pinctrl_i2c1_gpio: i2c1gpiogrp {
};
pinctrl_pmic: pmicgrp {
fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>;
fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1c4>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {

2
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
View File

@ -903,7 +903,7 @@ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x41
pinctrl_pmic: aristainetos3-pmic-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
View File

@ -1001,7 +1001,7 @@ MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0
pinctrl_pmic: pmic-grp {
fsl,pins = <
/* PMIC_nINT */
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
View File

@ -440,7 +440,7 @@ MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
View File

@ -499,7 +499,7 @@ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi
View File

@ -241,7 +241,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@ -989,7 +989,7 @@ MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
pinctrl_pmic: dhcom-pmic-grp {
fsl,pins = <
/* PMIC_nINT */
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi
View File

@ -563,7 +563,7 @@ MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x41 /* PCIE RST */
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
View File

@ -132,7 +132,7 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
View File

@ -356,7 +356,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi
View File

@ -296,7 +296,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x1c0
>;
};

4
arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
View File

@ -174,7 +174,7 @@ pmic: pmic@25 {
pinctrl-0 = <&pmic_pins>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
nxp,i2c-lt-enable;
regulators {
@ -417,7 +417,7 @@ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x160
pmic_pins: pinctrl-pmic-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};

4
arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts
View File

@ -275,7 +275,7 @@ pmic@25 {
reg = <0x25>;
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
/*
* i.MX 8M Plus Data Sheet for Consumer Products
@ -739,7 +739,7 @@ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40 /* NFC_INT */
pinctrl_pmic: pmic-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 /* #PMIC_INT */
>;
};

1
drivers/reset/amlogic/reset-meson.c
View File

@ -42,6 +42,7 @@ static const struct meson_reset_param meson_s4_param = {
};
static const struct meson_reset_param t7_param = {
.reset_ops = &meson_reset_ops,
.reset_num = 224,
.reset_offset = 0x0,
.level_offset = 0x40,