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mfd: max77759: Improve static struct formatting and commentary

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Improve code style. This includes the following:
- Formatting the max77759_chgr_irqs entries to fit in a single line
  instead of breaking them into multiple lines to improve readability.

- Refactoring comments such that they're full sentences and have
  punctuation marks for a couple of macro definitions to adhere to the
  documentation style.

- Explicitly initializing `MAX77759_CHGR_MODE_OFF`.

Signed-off-by: Amit Sunil Dhamne <amitsd@google.com>
Link: https://patch.msgid.link/20260504-fix-mfd-max77759-driver-v1-1-4d4a31a1d214@google.com
Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
Amit Sunil Dhamne 2026-05-04 22:49:54 +00:00 committed by Lee Jones
parent 5618127fed
commit 7b7b7fa42d
2 changed files with 19 additions and 35 deletions
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48
drivers/mfd/max77759.c
View File

@ -286,38 +286,22 @@ static const struct regmap_irq max77759_topsys_irqs[] = {
};
static const struct regmap_irq max77759_chgr_irqs[] = {
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0,
MAX77759_CHGR_REG_CHG_INT_AICL),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0,
MAX77759_CHGR_REG_CHG_INT_CHGIN),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0,
MAX77759_CHGR_REG_CHG_INT_WCIN),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0,
MAX77759_CHGR_REG_CHG_INT_CHG),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0,
MAX77759_CHGR_REG_CHG_INT_BAT),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0,
MAX77759_CHGR_REG_CHG_INT_INLIM),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0,
MAX77759_CHGR_REG_CHG_INT_THM2),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0,
MAX77759_CHGR_REG_CHG_INT_BYP),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1,
MAX77759_CHGR_REG_CHG_INT2_INSEL),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1,
MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1,
MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1,
MAX77759_CHGR_REG_CHG_INT2_BAT_OILO),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1,
MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1,
MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1,
MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1,
MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0, MAX77759_CHGR_REG_CHG_INT_AICL),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0, MAX77759_CHGR_REG_CHG_INT_CHGIN),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0, MAX77759_CHGR_REG_CHG_INT_WCIN),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0, MAX77759_CHGR_REG_CHG_INT_CHG),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0, MAX77759_CHGR_REG_CHG_INT_BAT),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0, MAX77759_CHGR_REG_CHG_INT_INLIM),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0, MAX77759_CHGR_REG_CHG_INT_THM2),
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0, MAX77759_CHGR_REG_CHG_INT_BYP),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1, MAX77759_CHGR_REG_CHG_INT2_INSEL),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1, MAX77759_CHGR_REG_CHG_INT2_BAT_OILO),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO),
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE),
};
static const struct regmap_irq_chip max77759_pmic_irq_chip = {

6
include/linux/mfd/max77759.h
View File

@ -106,9 +106,9 @@
#define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3
#define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4
#define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5
/* Wireless Charging input channel select */
/* Setting this enables the Wireless Charging input channel. */
#define MAX77759_CHGR_REG_CHG_CNFG_12_WCINSEL BIT(6)
/* CHGIN/USB input channel select */
/* Setting this enables the CHGIN/USB input channel. */
#define MAX77759_CHGR_REG_CHG_CNFG_12_CHGINSEL BIT(5)
#define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6
#define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7
@ -204,7 +204,7 @@ enum max77759_chgr_chg_dtls_states {
};
enum max77759_chgr_mode {
MAX77759_CHGR_MODE_OFF,
MAX77759_CHGR_MODE_OFF = 0x0,
MAX77759_CHGR_MODE_CHG_BUCK_ON = 0x5,
MAX77759_CHGR_MODE_OTG_BOOST_ON = 0xA,
};