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arm64: dts: add support for NXP i.MX95 15x15 audio board (version 2)
i.MX Audio Board is a configurable and functional audio processing platform. Integrating a variety of audio input and output interfaces into the system, the i.MX Audio Board supports HDMI input, HDMI eARC, S/PDIF I/O, 2-ch ADC line-in, 24-ch DAC line-out and more. Based on these features, rich audio application cases can be realized. This is a basic device tree supporting with i.MX95 15x15 SoC and Audio board (version 2). - Six Cortex-A55 - NXP PCAL6416 GPIO expanders - RGB LEDs via GPIO expander - LPI2C1, LPI2C2, LPI2C3 controllers - LPUART1 (console) - USDHC1 (eMMC), USDHC2 (SD) - Three DAC (AK4458) - One ADC (AK5552) Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Shengjiu Wang
Frank Li
parent
990c229608
commit
7b5d318616
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@ -502,6 +502,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-ab2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
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669
arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts
Normal file
669
arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts
Normal file
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@ -0,0 +1,669 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2024 NXP
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*/
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/dts-v1/;
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#include <dt-bindings/usb/pd.h>
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#include "imx95.dtsi"
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#define BRD_SM_CTRL_SD3_WAKE 0x8000
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#define BRD_SM_CTRL_PCIE1_WAKE 0x8001
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#define BRD_SM_CTRL_BT_WAKE 0x8002
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#define BRD_SM_CTRL_PCIE2_WAKE 0x8003
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#define BRD_SM_CTRL_BUTTON 0x8004
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/ {
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compatible = "fsl,imx95-15x15-ab2", "fsl,imx95";
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model = "NXP i.MX95 CPU on AB2";
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aliases {
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ethernet0 = &enetc_port0;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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i2c0 = &lpi2c1;
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i2c1 = &lpi2c2;
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i2c2 = &lpi2c3;
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i2c3 = &lpi2c4;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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serial0 = &lpuart1;
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};
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chosen {
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#address-cells = <2>;
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#size-cells = <2>;
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stdout-path = &lpuart1;
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};
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reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
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compatible = "regulator-fixed";
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regulator-name = "ab2_ana_pwr";
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regulator-always-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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gpio = <&pcal6524 1 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
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compatible = "regulator-fixed";
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regulator-name = "ab2_vdd_pwr_5v0";
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regulator-always-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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regulator-name = "VDD_SD2_3V3";
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off-on-delay-us = <12000>;
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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pinctrl-names = "default";
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reserved-memory {
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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linux_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x80000000 0 0x7f000000>;
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reusable;
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size = <0 0x3c000000>;
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linux,cma-default;
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};
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vpu_boot: vpu-boot@a0000000 {
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reg = <0 0xa0000000 0 0x100000>;
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no-map;
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};
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};
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sound-ak4458 {
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compatible = "fsl,imx-audio-card";
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model = "ak4458-audio";
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pri-dai-link {
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format = "i2s";
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link-name = "akcodec";
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fsl,mclk-equal-bclk;
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codec {
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sound-dai = <&ak4458_1>, <&ak4458_2>;
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};
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cpu {
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sound-dai = <&sai2>;
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};
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};
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};
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sound-ak5552 {
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compatible = "fsl,imx-audio-card";
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model = "ak5552-audio";
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pri-dai-link {
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format = "i2s";
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link-name = "akcodec";
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fsl,mclk-equal-bclk;
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codec {
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sound-dai = <&ak5552>;
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};
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cpu {
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sound-dai = <&sai3>;
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};
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};
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};
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sound-micfil {
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compatible = "fsl,imx-audio-card";
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model = "micfil-audio";
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pri-dai-link {
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format = "i2s";
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link-name = "micfil hifi";
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cpu {
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sound-dai = <&micfil>;
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};
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};
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};
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sound-xcvr {
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compatible = "fsl,imx-audio-card";
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model = "imx-audio-xcvr";
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pri-dai-link {
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link-name = "XCVR PCM";
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cpu {
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sound-dai = <&xcvr>;
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};
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};
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};
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memory@80000000 {
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reg = <0x0 0x80000000 0 0x80000000>;
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device_type = "memory";
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};
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};
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&enetc_port0 {
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phy-handle = <ðphy0>;
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phy-mode = "rgmii-id";
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pinctrl-0 = <&pinctrl_enetc0>;
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pinctrl-names = "default";
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status = "okay";
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};
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&lpi2c1 {
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clock-frequency = <400000>;
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pinctrl-0 = <&pinctrl_lpi2c1>;
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pinctrl-names = "default";
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status = "disabled";
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};
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&lpi2c2 {
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clock-frequency = <400000>;
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pinctrl-0 = <&pinctrl_lpi2c2>;
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pinctrl-names = "default";
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status = "okay";
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pcal6524: gpio@22 {
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compatible = "nxp,pcal6524";
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reg = <0x22>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gpio5>;
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interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
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#gpio-cells = <2>;
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gpio-controller;
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pinctrl-0 = <&pinctrl_pcal6524>;
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pinctrl-names = "default";
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};
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};
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&lpi2c3 {
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clock-frequency = <400000>;
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pinctrl-0 = <&pinctrl_lpi2c3>;
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pinctrl-names = "default";
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status = "okay";
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ak4458_1: audio-codec@10 {
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compatible = "asahi-kasei,ak4458";
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reg = <0x10>;
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#sound-dai-cells = <0>;
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AVDD-supply = <®_ab2_ana_pwr>;
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DVDD-supply = <®_ab2_ana_pwr>;
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reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>;
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sound-name-prefix = "0";
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};
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ak4458_3: audio-codec@11 {
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compatible = "asahi-kasei,ak4458";
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reg = <0x11>;
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#sound-dai-cells = <0>;
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AVDD-supply = <®_ab2_ana_pwr>;
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DVDD-supply = <®_ab2_ana_pwr>;
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reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>;
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status = "disabled";
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};
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ak4458_2: audio-codec@12 {
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compatible = "asahi-kasei,ak4458";
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reg = <0x12>;
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#sound-dai-cells = <0>;
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AVDD-supply = <®_ab2_ana_pwr>;
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DVDD-supply = <®_ab2_ana_pwr>;
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reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>;
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sound-name-prefix = "1";
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};
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ak5552: audio-codec@13 {
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compatible = "asahi-kasei,ak5552";
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reg = <0x13>;
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#sound-dai-cells = <0>;
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AVDD-supply = <®_ab2_ana_pwr>;
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DVDD-supply = <®_ab2_ana_pwr>;
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reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>;
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};
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pca6416: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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&lpi2c4 {
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clock-frequency = <400000>;
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pinctrl-0 = <&pinctrl_lpi2c4>;
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pinctrl-names = "default";
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status = "okay";
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};
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&lpuart1 {
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/* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&micfil {
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assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2>,
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<&scmi_clk IMX95_CLK_PDM>;
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assigned-clock-parents = <0>, <0>, <0>, <0>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>;
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assigned-clock-rates = <3932160000>,
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<3612672000>, <393216000>,
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<361267200>, <49152000>;
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#sound-dai-cells = <0>;
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pinctrl-0 = <&pinctrl_pdm>;
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pinctrl-names = "default";
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status = "okay";
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};
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&netc_blk_ctrl {
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status = "okay";
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};
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&netc_emdio {
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pinctrl-0 = <&pinctrl_emdio>;
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pinctrl-names = "default";
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status = "okay";
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ethphy0: ethernet-phy@1 {
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reg = <1>;
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reset-assert-us = <10000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&pcal6524 4 GPIO_ACTIVE_LOW>;
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realtek,clkout-disable;
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};
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};
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&netcmix_blk_ctrl {
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status = "okay";
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};
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&sai2 {
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clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>,
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<&scmi_clk IMX95_CLK_SAI2>, <&dummy>,
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<&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
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assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2>,
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<&scmi_clk IMX95_CLK_SAI2>;
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assigned-clock-parents = <0>, <0>, <0>, <0>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>;
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assigned-clock-rates = <3932160000>,
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<3612672000>, <393216000>,
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<361267200>, <12288000>;
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#sound-dai-cells = <0>;
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pinctrl-0 = <&pinctrl_sai2>;
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pinctrl-names = "default";
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fsl,sai-asynchronous;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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&sai3 {
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clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>,
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<&scmi_clk IMX95_CLK_SAI3>, <&dummy>,
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<&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
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assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2>,
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<&scmi_clk IMX95_CLK_SAI3>;
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assigned-clock-parents = <0>, <0>, <0>, <0>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>;
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assigned-clock-rates = <3932160000>,
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<3612672000>, <393216000>,
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<361267200>, <12288000>;
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#sound-dai-cells = <0>;
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pinctrl-0 = <&pinctrl_sai3>;
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pinctrl-names = "default";
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fsl,sai-asynchronous;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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&sai5 {
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assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2>,
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<&scmi_clk IMX95_CLK_SAI5>;
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assigned-clock-parents = <0>, <0>, <0>, <0>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>;
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assigned-clock-rates = <3932160000>,
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<3612672000>, <393216000>,
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<361267200>, <12288000>;
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#sound-dai-cells = <0>;
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pinctrl-0 = <&pinctrl_sai5>;
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pinctrl-names = "default";
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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&scmi_iomuxc {
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pinctrl_emdio: emdiogrp {
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fsl,pins = <
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IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e
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IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e
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>;
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};
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pinctrl_enetc0: enetc0grp {
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fsl,pins = <
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IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e
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IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e
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IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e
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IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e
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IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
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IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
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IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
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IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e
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IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e
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IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e
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IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e
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IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e
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IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e
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>;
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};
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|
||||
pinctrl_lpi2c2: lpi2c2grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e
|
||||
IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lpi2c3: lpi2c3grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
|
||||
IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lpi2c4: lpi2c4grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e
|
||||
IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcal6524: pcal6524grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pdm: pdmgrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e
|
||||
IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e
|
||||
IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x31e
|
||||
IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x31e
|
||||
IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e
|
||||
IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e
|
||||
IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e
|
||||
IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e
|
||||
IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e
|
||||
IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x31e
|
||||
IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x31e
|
||||
IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e
|
||||
IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e
|
||||
IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e
|
||||
IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e
|
||||
IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e
|
||||
IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e
|
||||
IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x31e
|
||||
IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x31e
|
||||
IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x31e
|
||||
IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai3: sai3grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e
|
||||
IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e
|
||||
IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e
|
||||
IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai5: sai5grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x31e
|
||||
IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x31e
|
||||
IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x31e
|
||||
IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x31e
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spdif: spdifgrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_GPIO_IO22__SPDIF_IN 0x31e
|
||||
IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
|
||||
IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
|
||||
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
|
||||
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
|
||||
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
|
||||
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
|
||||
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
|
||||
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
|
||||
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
|
||||
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
|
||||
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
|
||||
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
|
||||
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
|
||||
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
|
||||
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
|
||||
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
|
||||
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
|
||||
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
|
||||
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
|
||||
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
|
||||
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
|
||||
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
|
||||
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
|
||||
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
|
||||
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
|
||||
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
|
||||
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
|
||||
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
|
||||
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
|
||||
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
|
||||
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
|
||||
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
|
||||
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
|
||||
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
|
||||
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
|
||||
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
|
||||
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
|
||||
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
|
||||
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
|
||||
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
|
||||
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
|
||||
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
|
||||
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
|
||||
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
|
||||
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
|
||||
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
|
||||
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
|
||||
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
|
||||
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
|
||||
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&scmi_misc {
|
||||
nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1>,
|
||||
<BRD_SM_CTRL_PCIE1_WAKE 1>,
|
||||
<BRD_SM_CTRL_BT_WAKE 1>,
|
||||
<BRD_SM_CTRL_PCIE2_WAKE 1>,
|
||||
<BRD_SM_CTRL_BUTTON 1>;
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_dwc3 {
|
||||
adp-disable;
|
||||
dr_mode = "host";
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
pinctrl-3 = <&pinctrl_usdhc1>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
||||
fsl,tuning-step = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xcvr {
|
||||
clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
|
||||
<&scmi_clk IMX95_CLK_SPDIF>,
|
||||
<&dummy>,
|
||||
<&scmi_clk IMX95_CLK_AUDIOXCVR>,
|
||||
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
|
||||
<&scmi_clk IMX95_CLK_AUDIOPLL2>;
|
||||
clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k";
|
||||
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
|
||||
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
|
||||
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
|
||||
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
|
||||
<&scmi_clk IMX95_CLK_SPDIF>,
|
||||
<&scmi_clk IMX95_CLK_AUDIOXCVR>;
|
||||
assigned-clock-parents = <0>, <0>, <0>, <0>,
|
||||
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
|
||||
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
|
||||
assigned-clock-rates = <3932160000>, <3612672000>,
|
||||
<393216000>, <361267200>,
|
||||
<12288000>, <0>;
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-0 = <&pinctrl_spdif>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user