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This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 5.18, please pull the following: - Krzysztof aligns the PL330 DMA controller node name to the schema - Rafal corrects the TWD (Timer/Watchdog) block, adds the watchdog node, I2C controller node and the pinctrl node for the 4908 SoC - Kuldeep fixes the Northstar 2 SPI properties as well as the PL022 SPI controller clock names - Frank fixes the SATA node names to conform to the AHCI controller schema -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmImX64ACgkQh9CWnEQH BwRKhQ//RUIUtJqWOZNMkvspu2VaIOa4DeDFXHQ2F8X7hoRsRw93mksxk90xBuIG Oz4UdzF5D0cKwXdlNWeJ3V8er6qSkl5V37Z0iBUft6n1vYiqPzQHAG7lvI3r0ZNX Ial9H1TLuT36CeubcUlb88ztPvMZYDPoUDFQv8GKoavGldwMithoHe6SZ3SFGFVh /lzRyqJImJR3wITZJboLdyqkUvksj1lofR0kRM25bNZ1QeDxzEdA48svZYnexnGh PNPGvuhNlT63CBSdteXs5lU2pmt6OhaxUH6Vl9dWE5LznqCrEPAlSy6jiNsymgHp GqijueWGQyVQYqCE2T0VNowCTLY1a3bl7rFQUigZLCurbqYr932GwZP+r/1/xfqI pP96QjA/Fz4fjuH9yZ30dTCB3xe69GurM80V3udNi1nr8ExDjOY/3rmrEmKVLKDR Y94wgzjgzy1Wopvnzu9CtlabixQ7sv0NLJB6YjSSqc+ziBZsnJOl0+b7hWaBTuno UxBY3pIsekBg4MP6evPHs8muUHO9STXijDwnny6tNj5o/usGrfWIBtilNYnAYg/1 /3UWnDArcV+/zpRhIwsAwYb19pUBOQCpKFLdZYw4yNss12KLqxvmA3fe6JXAu9HF bmCUEjAwuf3mtEN41V8Tjyp3ftuh7rO3VVjDuT72VfYiEh2QtKU= =nJaL -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIndl0ACgkQmmx57+YA GNk5PhAAxL+CTTI8nidIhzO5kO/KZ4NIb7LO/QnMWknn+HeUdXPl0GDRyIpsXml9 X5qcIzL4Npj0U8+UAHYarT6ngDcj8EZDWv+H5zRmt5qXSNhpfnlm+1OEgicy8Y1u XwgIfLtGbdE9w05i9fPPtSIjoAjMQpJEplOkKKzex3k8GN653dT8bLm/manevoL7 7Sn27jxfQUcRM10QOJcWmF1fqgdl542J31bE4xl1axXww1Fa6aoZAXeeh+XlO8KB oXJhcw4HLW7LKpZUESCwTiXS7fymSgp73U2bRhr41g40BPzt8wJbmS5MMsY7eiLP 9+kgfswtDrNt5NBDHFye71bU1YXvIAdcWkexlJfio8bsv8HweS+hU61+jpULpbtp EzttCHoljyyAIpnjOMe7mrQKsm4hTnTcB0vKBgZqpxAlLZaoKcrkknfZz57nwcHL xLtkug5lEp6jIXtAAQAYZ5ZwkQCUo4oaHlN16DypGvAsvSUd3UjQbLJBtfb7joac wQ8stJQGhMcSzjyiOAEwSHqJeau9uJ03xWHrKNYPAx8aj5eVtNLMXxNcq69mzMvb BbDUt8SMedxxficxteZfC3tkoH6CQ+zOHSEAzm/A+Q0GvJkxOkyDt6IW+BE30bGE vDzfJmwBrf2N8FhnkbJsob+vlWZuAz4ezM5q8i4zHx6U2MoSc3I= =B+QM -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-5.18/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt This pull request contains Broadcom ARM64-based SoCs Device Tree updates for 5.18, please pull the following: - Krzysztof aligns the PL330 DMA controller node name to the schema - Rafal corrects the TWD (Timer/Watchdog) block, adds the watchdog node, I2C controller node and the pinctrl node for the 4908 SoC - Kuldeep fixes the Northstar 2 SPI properties as well as the PL022 SPI controller clock names - Frank fixes the SATA node names to conform to the AHCI controller schema * tag 'arm-soc/for-5.18/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: stingray: Fix spi clock name arm64: dts: ns2: Fix spi clock name arm64: dts: broadcom: Fix sata nodename arm64: dts: ns2: Fix spi-cpol and spi-cpha property arm64: dts: broadcom: bcm4908: add I2C block arm64: dts: broadcom: bcm4908: add watchdog block arm64: dts: broadcom: bcm4908: add pinctrl binding arm64: dts: broadcom: bcm4908: use proper TWD binding arm64: dts: broadcom: align pl330 node name with dtschema Link: https://lore.kernel.org/r/20220307194817.3754107-3-f.fainelli@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
7b4fc7c6f9
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@ -273,9 +273,18 @@ bus@ff800000 {
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#size-cells = <1>;
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ranges = <0x00 0x00 0xff800000 0x3000>;
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timer: timer@400 {
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compatible = "brcm,bcm6328-timer", "syscon";
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reg = <0x400 0x3c>;
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twd: timer-mfd@400 {
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compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
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reg = <0x400 0x4c>;
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ranges = <0x0 0x400 0x4c>;
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#address-cells = <1>;
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#size-cells = <1>;
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watchdog@28 {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x28 0x8>;
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};
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};
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gpio0: gpio-controller@500 {
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@ -287,6 +296,141 @@ gpio0: gpio-controller@500 {
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gpio-controller;
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};
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pinctrl@560 {
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compatible = "brcm,bcm4908-pinctrl";
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reg = <0x560 0x10>;
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pins_led_0_a: led_0-a-pins {
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function = "led_0";
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groups = "led_0_grp_a";
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};
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pins_led_1_a: led_1-a-pins {
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function = "led_1";
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groups = "led_1_grp_a";
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};
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pins_led_2_a: led_2-a-pins {
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function = "led_2";
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groups = "led_2_grp_a";
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};
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pins_led_3_a: led_3-a-pins {
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function = "led_3";
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groups = "led_3_grp_a";
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};
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pins_led_4_a: led_4-a-pins {
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function = "led_4";
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groups = "led_4_grp_a";
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};
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pins_led_5_a: led_5-a-pins {
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function = "led_5";
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groups = "led_5_grp_a";
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};
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pins_led_6_a: led_6-a-pins {
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function = "led_6";
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groups = "led_6_grp_a";
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};
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pins_led_7_a: led_7-a-pins {
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function = "led_7";
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groups = "led_7_grp_a";
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};
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pins_led_8_a: led_8-a-pins {
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function = "led_8";
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groups = "led_8_grp_a";
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};
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pins_led_9_a: led_9-a-pins {
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function = "led_9";
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groups = "led_9_grp_a";
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};
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pins_led_21_a: led_21-a-pins {
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function = "led_21";
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groups = "led_21_grp_a";
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};
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pins_led_22_a: led_22-a-pins {
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function = "led_22";
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groups = "led_22_grp_a";
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};
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pins_led_26_a: led_26-a-pins {
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function = "led_26";
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groups = "led_26_grp_a";
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};
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pins_led_27_a: led_27-a-pins {
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function = "led_27";
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groups = "led_27_grp_a";
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};
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pins_led_28_a: led_28-a-pins {
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function = "led_28";
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groups = "led_28_grp_a";
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};
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pins_led_29_a: led_29-a-pins {
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function = "led_29";
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groups = "led_29_grp_a";
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};
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pins_led_30_a: led_30-a-pins {
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function = "led_30";
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groups = "led_30_grp_a";
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};
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pins_hs_uart: hs_uart-pins {
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function = "hs_uart";
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groups = "hs_uart_grp";
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};
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pins_i2c_a: i2c-a-pins {
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function = "i2c";
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groups = "i2c_grp_a";
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};
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pins_i2c_b: i2c-b-pins {
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function = "i2c";
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groups = "i2c_grp_b";
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};
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pins_i2s: i2s-pins {
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function = "i2s";
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groups = "i2s_grp";
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};
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pins_nand_ctrl: nand_ctrl-pins {
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function = "nand_ctrl";
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groups = "nand_ctrl_grp";
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};
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pins_nand_data: nand_data-pins {
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function = "nand_data";
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groups = "nand_data_grp";
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};
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pins_emmc_ctrl: emmc_ctrl-pins {
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function = "emmc_ctrl";
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groups = "emmc_ctrl_grp";
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};
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pins_usb0_pwr: usb0_pwr-pins {
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function = "usb0_pwr";
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groups = "usb0_pwr_grp";
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};
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pins_usb1_pwr: usb1_pwr-pins {
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function = "usb1_pwr";
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groups = "usb1_pwr_grp";
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};
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};
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uart0: serial@640 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x640 0x18>;
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@ -312,6 +456,15 @@ nandcs: nand@0 {
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};
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};
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i2c@2100 {
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compatible = "brcm,brcmper-i2c";
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reg = <0x2100 0x58>;
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clock-frequency = <97500>;
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pinctrl-names = "default";
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pinctrl-0 = <&pins_i2c_a>;
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status = "disabled";
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};
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misc@2600 {
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compatible = "brcm,misc", "simple-mfd";
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reg = <0x2600 0xe4>;
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@ -330,7 +483,7 @@ reset-controller@2644 {
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reboot {
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compatible = "syscon-reboot";
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regmap = <&timer>;
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regmap = <&twd>;
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offset = <0x34>;
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mask = <1>;
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};
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@ -111,8 +111,8 @@ slic@0 {
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compatible = "silabs,si3226x";
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reg = <0>;
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spi-max-frequency = <5000000>;
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spi-cpha = <1>;
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spi-cpol = <1>;
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spi-cpha;
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spi-cpol;
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pl022,hierarchy = <0>;
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pl022,interface = <0>;
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pl022,slave-tx-disable = <0>;
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@ -135,8 +135,8 @@ at25@0 {
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at25,byte-len = <0x8000>;
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at25,addr-mode = <2>;
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at25,page-size = <64>;
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spi-cpha = <1>;
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spi-cpol = <1>;
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spi-cpha;
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spi-cpol;
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pl022,hierarchy = <0>;
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pl022,interface = <0>;
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pl022,slave-tx-disable = <0>;
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@ -276,7 +276,7 @@ crypto3: crypto@61330000 {
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mboxes = <&pdc3 0>;
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};
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dma0: dma@61360000 {
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dma0: dma-controller@61360000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x61360000 0x1000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
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@ -644,7 +644,7 @@ ssp0: spi@66180000 {
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reg = <0x66180000 0x1000>;
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interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>, <&iprocslow>;
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clock-names = "spiclk", "apb_pclk";
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clock-names = "sspclk", "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -655,7 +655,7 @@ ssp1: spi@66190000 {
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reg = <0x66190000 0x1000>;
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interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>, <&iprocslow>;
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clock-names = "spiclk", "apb_pclk";
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clock-names = "sspclk", "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -687,7 +687,7 @@ sata_phy1: sata-phy@1 {
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};
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};
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sata: ahci@663f2000 {
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sata: sata@663f2000 {
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compatible = "brcm,iproc-ahci", "generic-ahci";
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reg = <0x663f2000 0x1000>;
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dma-coherent;
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@ -519,7 +519,7 @@ ssp0: spi@180000 {
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reg = <0x00180000 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
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clock-names = "spiclk", "apb_pclk";
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clock-names = "sspclk", "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -531,7 +531,7 @@ ssp1: spi@190000 {
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reg = <0x00190000 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
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clock-names = "spiclk", "apb_pclk";
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clock-names = "sspclk", "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -543,7 +543,7 @@ hwrng: hwrng@220000 {
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reg = <0x00220000 0x28>;
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};
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dma0: dma@310000 {
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dma0: dma-controller@310000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x00310000 0x1000>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
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