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coresight: Make clock sequence consistent
Since atclk is enabled after pclk during the probe phase, this commit maintains the same sequence for the runtime resume flow. Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com> Tested-by: James Clark <james.clark@linaro.org> Signed-off-by: Leo Yan <leo.yan@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20250731-arm_cs_fix_clock_v4-v6-9-1dfe10bb3f6f@arm.com
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@ -297,11 +297,11 @@ static int funnel_runtime_resume(struct device *dev)
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{
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struct funnel_drvdata *drvdata = dev_get_drvdata(dev);
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if (drvdata && !IS_ERR(drvdata->atclk))
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clk_prepare_enable(drvdata->atclk);
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if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
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clk_prepare_enable(drvdata->pclk);
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if (drvdata && !IS_ERR(drvdata->atclk))
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clk_prepare_enable(drvdata->atclk);
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return 0;
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}
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#endif
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@ -335,11 +335,11 @@ static int replicator_runtime_resume(struct device *dev)
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{
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struct replicator_drvdata *drvdata = dev_get_drvdata(dev);
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if (drvdata && !IS_ERR(drvdata->atclk))
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clk_prepare_enable(drvdata->atclk);
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if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
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clk_prepare_enable(drvdata->pclk);
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if (drvdata && !IS_ERR(drvdata->atclk))
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clk_prepare_enable(drvdata->atclk);
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return 0;
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}
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#endif
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@ -969,11 +969,11 @@ static int stm_runtime_resume(struct device *dev)
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{
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struct stm_drvdata *drvdata = dev_get_drvdata(dev);
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if (drvdata && !IS_ERR(drvdata->atclk))
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clk_prepare_enable(drvdata->atclk);
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if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
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clk_prepare_enable(drvdata->pclk);
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if (drvdata && !IS_ERR(drvdata->atclk))
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clk_prepare_enable(drvdata->atclk);
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return 0;
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}
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#endif
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@ -218,11 +218,11 @@ static int tpiu_runtime_resume(struct device *dev)
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{
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struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
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if (drvdata && !IS_ERR(drvdata->atclk))
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clk_prepare_enable(drvdata->atclk);
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if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
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clk_prepare_enable(drvdata->pclk);
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if (drvdata && !IS_ERR(drvdata->atclk))
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clk_prepare_enable(drvdata->atclk);
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return 0;
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}
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#endif
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