github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-06 05:27:07 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC

Browse Source 
Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus mode
to config the eMMC work at HS400ES mode.

Also update to use Standard Drive Strength for USDHC pad to get a better
signal quality per Hardware team suggests.

Reviewed-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Haibo Chen 2023-07-24 15:58:32 +08:00 committed by Shawn Guo
parent 3d25633036
commit 7adf8410cb
1 changed files with 14 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
View File

@ -119,9 +119,11 @@ &lpuart5 {
};
&usdhc0 {
pinctrl-names = "default", "sleep";
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>;
pinctrl-3 = <&pinctrl_usdhc0>;
non-removable;
bus-width = <8>;
status = "okay";
@ -200,17 +202,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
MX8ULP_PAD_PTD10__SDHC0_D0 0x43
MX8ULP_PAD_PTD9__SDHC0_D1 0x43
MX8ULP_PAD_PTD8__SDHC0_D2 0x43
MX8ULP_PAD_PTD7__SDHC0_D3 0x43
MX8ULP_PAD_PTD6__SDHC0_D4 0x43
MX8ULP_PAD_PTD5__SDHC0_D5 0x43
MX8ULP_PAD_PTD4__SDHC0_D6 0x43
MX8ULP_PAD_PTD3__SDHC0_D7 0x43
MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
MX8ULP_PAD_PTD10__SDHC0_D0 0x3
MX8ULP_PAD_PTD9__SDHC0_D1 0x3
MX8ULP_PAD_PTD8__SDHC0_D2 0x3
MX8ULP_PAD_PTD7__SDHC0_D3 0x3
MX8ULP_PAD_PTD6__SDHC0_D4 0x3
MX8ULP_PAD_PTD5__SDHC0_D5 0x3
MX8ULP_PAD_PTD4__SDHC0_D6 0x3
MX8ULP_PAD_PTD3__SDHC0_D7 0x3
MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
>;
};
};