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drm/i915/display: Add PHY_CMN1_CONTROL register definitions

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Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS
sending.

Bspec: 68962
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250526120512.1702815-10-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander 2025-05-26 15:05:09 +03:00
parent 6ecb8e586f
commit 7acc76a37e
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
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@ -285,6 +285,9 @@
#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
#define PHY_CMN1_CONTROL(tx, control) (0x800 + ((tx) - 1) * 0x200 + (control))
#define CONTROL0_MAC_TRANSMIT_LFPS REG_BIT(1)
/* C20 Registers */
#define PHY_C20_WR_ADDRESS_L 0xC02
#define PHY_C20_WR_ADDRESS_H 0xC03