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PCI: rockchip: dw: Support BAR4 for standard ep
Change-Id: Ia6182f410681b76f2d7c8225d0d8467c5664452f Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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@ -482,23 +482,26 @@ static void rockchip_pcie_resize_bar(struct rockchip_pcie *rockchip)
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resbar_base = rockchip_pci_find_resbar_capability(rockchip);
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/* Resize BAR0 4M 32bits, BAR2 64M 64bits-pref */
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bar = 0;
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bar = BAR_0;
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dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
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dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x2c0);
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rockchip_pcie_ep_set_bar_flag(rockchip, BAR_0, PCI_BASE_ADDRESS_MEM_TYPE_32);
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rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
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bar = 2;
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bar = BAR_2;
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dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
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dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x6c0);
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rockchip_pcie_ep_set_bar_flag(rockchip, BAR_2,
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rockchip_pcie_ep_set_bar_flag(rockchip, bar,
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PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
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bar = BAR_4;
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dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
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dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0xc0);
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rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
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/* Disable BAR1 BAR4 BAR5*/
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bar = 1;
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bar = BAR_1;
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dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
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bar = 4;
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dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
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bar = 5;
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bar = BAR_5;
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dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
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}
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