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clk: spacemit: k3: fix parent clock of UFS aclk

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According to SpacemiT updated clock docs, the previous UFS aclk parent
clock was wrong, the correct one is illustrated below, so fix it.

  --> pll1_d5_491p52 --\
  --> pll1_d6_409p6  --|
  --> pll2_d6        --|--> div --> gate --> ufs_aclk
  --> pll2_d5        --/

Fixes: e371a77255 ("clk: spacemit: k3: add the clock tree")
Link: https://patch.msgid.link/20260630-06-clk-ufs-support-v1-1-cf7521d1d0fe@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
This commit is contained in:
Yixun Lan 2026-06-30 12:52:45 +00:00
parent dc59e4fea9
commit 7a588b6267
1 changed files with 3 additions and 4 deletions
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7
drivers/clk/spacemit/ccu-k3.c
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@ -926,11 +926,10 @@ CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 1
20, 3, BIT(16), 0);
static const struct clk_parent_data ufs_aclk_parents[] = {
CCU_PARENT_HW(pll1_d6_409p6),
CCU_PARENT_HW(pll1_d5_491p52),
CCU_PARENT_HW(pll1_d4_614p4),
CCU_PARENT_HW(pll1_d8_307p2),
CCU_PARENT_HW(pll2_d4),
CCU_PARENT_HW(pll1_d6_409p6),
CCU_PARENT_HW(pll2_d6),
CCU_PARENT_HW(pll2_d5),
};
CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8),
2, 3, BIT(1), 0);