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drm/i915/bw: Update bw calculation to account for 16 channels
Wa_16030862157: Update Bandwidth Calculation to account for 16channel memory config. v2: Logical separation of changes (Suraj, Vinod) WA: 16030862157, 16030875223 Bspec: 69131, 68859 Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/20260715143243.4141208-3-uma.shankar@intel.com
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@ -14,6 +14,7 @@
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#include "intel_display_regs.h"
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#include "intel_display_types.h"
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#include "intel_display_utils.h"
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#include "intel_display_wa.h"
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#include "intel_dram.h"
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#include "intel_mchbar.h"
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#include "intel_parent.h"
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@ -272,7 +273,14 @@ static int icl_init_qgv_info(struct intel_display *display,
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case INTEL_DRAM_LPDDR4:
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case INTEL_DRAM_LPDDR5:
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qi->t_bl = 16;
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qi->max_numchannels = 8;
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/*
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* Wa_16030862157
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* Xe3p supports a fully-populated 16-channel LPDDR
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* config (4 memory controllers x 4 channels); earlier
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* D14+ platforms top out at 8.
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*/
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qi->max_numchannels =
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intel_display_wa(display, INTEL_DISPLAY_WA_16030862157) ? 16 : 8;
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qi->channel_width = 16;
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qi->deinterleave = 4;
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break;
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@ -666,10 +674,16 @@ static int tgl_get_bw_info(struct intel_display *display,
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ipqdepth = min(ipqdepthpch, display_bw_params->displayrtids / num_channels);
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/*
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* Wa_16030862157
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* clperchgroup = 4kpagespermempage * clperchperblock,
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* clperchperblock = 8 / num_channels * interleave
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* clperchperblock = max(8 / num_channels, 1) * interleave
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*
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* The 8 / num_channels truncating divide collapses to 0 for
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* >8-channel configs (16-channel: 8 / 16 = 0); the max(..., 1) floor
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* keeps clperchperblock >= 1 there while preserving the literal
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* truncating divide for <=8-channel configs.
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*/
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clperchgroup = 4 * (8 / num_channels) * qi.deinterleave;
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clperchgroup = 4 * max(8 / num_channels, 1) * qi.deinterleave;
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display->bw.num_qgv_points = qi.num_qgv_points;
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display->bw.num_psf_gv_points = qi.num_psf_points;
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