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Microchip clock updates for v6.9
Polarfire: - MSSPLL hardware has 4 output clocks (the driver supported previously only one output); each of these 4 outputs feed dividers and the output of each divider feed individual hardware blocks (e.g. CAN, Crypto, eMMC); individual hardware block drivers need to control there clocks thus clock driver support was added for all MSSPLL output clocks. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCZeq6CgAKCRCejrg/N2X7 /bCeAP0V3t0Hq/6spRqBHpPELN89xBGGNNOicUgbQRO7DbO+jgEAjynG5b7m4a7O uENJezIxboPEsl59wkhHCR4u7mfS1Ak= =oSTT -----END PGP SIGNATURE----- Merge tag 'clk-microchip-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clk driver updates from Claudiu Beznea: Polarfire: - MSSPLL hardware has 4 output clocks (the driver supported previously only one output); each of these 4 outputs feed dividers and the output of each divider feed individual hardware blocks (e.g. CAN, Crypto, eMMC); individual hardware block drivers need to control their clocks thus clock driver support was added for all MSSPLL output clocks. * tag 'clk-microchip-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: microchip: mpfs: convert MSSPLL outputs to clk_divider clk: microchip: mpfs: add missing MSSPLL outputs clk: microchip: mpfs: setup for using other mss pll outputs clk: microchip: mpfs: split MSSPLL in two dt-bindings: can: mpfs: add missing required clock dt-bindings: clock: mpfs: add more MSSPLL output definitions
This commit is contained in:
Stephen Boyd
commit
7a1b0e9d81
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@ -24,7 +24,9 @@ properties:
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maxItems: 1
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clocks:
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maxItems: 1
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items:
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- description: AHB peripheral clock
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- description: CAN bus clock
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required:
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- compatible
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@ -39,7 +41,7 @@ examples:
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can@2010c000 {
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compatible = "microchip,mpfs-can";
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reg = <0x2010c000 0x1000>;
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clocks = <&clkcfg 17>;
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clocks = <&clkcfg 17>, <&clkcfg 37>;
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interrupt-parent = <&plic>;
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interrupts = <56>;
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};
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@ -15,7 +15,8 @@
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/* address offset of control registers */
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#define REG_MSSPLL_REF_CR 0x08u
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#define REG_MSSPLL_POSTDIV_CR 0x10u
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#define REG_MSSPLL_POSTDIV01_CR 0x10u
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#define REG_MSSPLL_POSTDIV23_CR 0x14u
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#define REG_MSSPLL_SSCG_2_CR 0x2Cu
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#define REG_CLOCK_CONFIG_CR 0x08u
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#define REG_RTC_CLOCK_CR 0x0Cu
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@ -26,10 +27,18 @@
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#define MSSPLL_FBDIV_WIDTH 0x0Cu
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#define MSSPLL_REFDIV_SHIFT 0x08u
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#define MSSPLL_REFDIV_WIDTH 0x06u
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#define MSSPLL_POSTDIV_SHIFT 0x08u
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#define MSSPLL_POSTDIV02_SHIFT 0x08u
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#define MSSPLL_POSTDIV13_SHIFT 0x18u
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#define MSSPLL_POSTDIV_WIDTH 0x07u
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#define MSSPLL_FIXED_DIV 4u
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/*
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* This clock ID is defined here, rather than the binding headers, as it is an
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* internal clock only, and therefore has no consumers in other peripheral
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* blocks.
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*/
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#define CLK_MSSPLL_INTERNAL 38u
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struct mpfs_clock_data {
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struct device *dev;
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void __iomem *base;
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@ -39,17 +48,27 @@ struct mpfs_clock_data {
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struct mpfs_msspll_hw_clock {
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void __iomem *base;
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struct clk_hw hw;
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struct clk_init_data init;
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unsigned int id;
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u32 reg_offset;
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u32 shift;
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u32 width;
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u32 flags;
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struct clk_hw hw;
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struct clk_init_data init;
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};
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#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
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struct mpfs_msspll_out_hw_clock {
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void __iomem *base;
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struct clk_divider output;
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struct clk_init_data init;
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unsigned int id;
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u32 reg_offset;
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};
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#define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw)
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struct mpfs_cfg_hw_clock {
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struct clk_divider cfg;
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struct clk_init_data init;
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@ -93,93 +112,40 @@ static const struct clk_div_table mpfs_div_rtcref_table[] = {
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{ 0, 0 }
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};
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/*
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* MSS PLL internal clock
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*/
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static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate)
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{
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struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
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void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
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void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
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void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
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u32 mult, ref_div, postdiv;
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mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
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mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
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ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
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ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
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postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT;
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postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH);
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return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv);
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}
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static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
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{
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struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
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void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
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void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
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u32 mult, ref_div;
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unsigned long rate_before_ctrl;
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mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
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mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
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ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
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ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
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rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
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return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
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msspll_hw->flags);
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}
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static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
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{
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struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
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void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
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void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
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void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
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u32 mult, ref_div, postdiv;
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int divider_setting;
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unsigned long rate_before_ctrl, flags;
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mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
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mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
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ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
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ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
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rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
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divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
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msspll_hw->flags);
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if (divider_setting < 0)
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return divider_setting;
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spin_lock_irqsave(&mpfs_clk_lock, flags);
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postdiv = readl_relaxed(postdiv_addr);
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postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT);
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writel_relaxed(postdiv, postdiv_addr);
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spin_unlock_irqrestore(&mpfs_clk_lock, flags);
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return 0;
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return prate * mult / (ref_div * MSSPLL_FIXED_DIV);
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}
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static const struct clk_ops mpfs_clk_msspll_ops = {
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.recalc_rate = mpfs_clk_msspll_recalc_rate,
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.round_rate = mpfs_clk_msspll_round_rate,
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.set_rate = mpfs_clk_msspll_set_rate,
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};
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#define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \
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.id = _id, \
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.flags = _flags, \
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.shift = _shift, \
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.width = _width, \
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.reg_offset = _offset, \
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.flags = _flags, \
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.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \
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}
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static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
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CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT,
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CLK_PLL(CLK_MSSPLL_INTERNAL, "clk_msspll_internal", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT,
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MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR),
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};
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@ -196,7 +162,7 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c
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ret = devm_clk_hw_register(dev, &msspll_hw->hw);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
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CLK_MSSPLL);
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CLK_MSSPLL_INTERNAL);
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data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw;
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}
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@ -204,6 +170,54 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c
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return 0;
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}
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/*
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* MSS PLL output clocks
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*/
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#define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \
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.id = _id, \
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.output.shift = _shift, \
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.output.width = _width, \
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.output.table = NULL, \
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.reg_offset = _offset, \
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.output.flags = _flags, \
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.output.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
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.output.lock = &mpfs_clk_lock, \
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}
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static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = {
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CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
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MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR),
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CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
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MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR),
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CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
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MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR),
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CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
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MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR),
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};
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static int mpfs_clk_register_msspll_outs(struct device *dev,
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struct mpfs_msspll_out_hw_clock *msspll_out_hws,
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unsigned int num_clks, struct mpfs_clock_data *data)
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{
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unsigned int i;
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int ret;
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for (i = 0; i < num_clks; i++) {
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struct mpfs_msspll_out_hw_clock *msspll_out_hw = &msspll_out_hws[i];
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msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset;
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ret = devm_clk_hw_register(dev, &msspll_out_hw->output.hw);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register msspll out id: %d\n",
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msspll_out_hw->id);
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data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->output.hw;
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}
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return 0;
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}
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/*
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* "CFG" clocks
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*/
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@ -442,8 +456,8 @@ static int mpfs_clk_probe(struct platform_device *pdev)
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int ret;
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/* CLK_RESERVED is not part of clock arrays, so add 1 */
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num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks)
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+ ARRAY_SIZE(mpfs_periph_clks) + 1;
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num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_msspll_out_clks)
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+ ARRAY_SIZE(mpfs_cfg_clks) + ARRAY_SIZE(mpfs_periph_clks) + 1;
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clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL);
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if (!clk_data)
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@ -466,6 +480,12 @@ static int mpfs_clk_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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ret = mpfs_clk_register_msspll_outs(dev, mpfs_msspll_out_clks,
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ARRAY_SIZE(mpfs_msspll_out_clks),
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clk_data);
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if (ret)
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return ret;
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ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data);
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if (ret)
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return ret;
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@ -44,6 +44,11 @@
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#define CLK_RTCREF 33
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#define CLK_MSSPLL 34
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#define CLK_MSSPLL0 34
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#define CLK_MSSPLL1 35
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#define CLK_MSSPLL2 36
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#define CLK_MSSPLL3 37
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/* 38 is reserved for MSS PLL internals */
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/* Clock Conditioning Circuitry Clock IDs */
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