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drm/xe/sr: Apply masked registers properly

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The 'clear' field for register save/restore entries was being placed in
the value bits of the register rather than the mask bits; make sure it
gets shifted into the mask bits.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230419224909.4000920-1-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-04-19 15:49:09 -07:00 committed by Rodrigo Vivi
parent fa4fe0db08
commit 79f2432e31
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/xe/xe_reg_sr.c
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@ -148,7 +148,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
* supposed to set all bits.
*/
if (entry->masked_reg)
val = (entry->clr_bits ?: entry->set_bits << 16);
val = (entry->clr_bits ?: entry->set_bits) << 16;
else if (entry->clr_bits + 1)
val = (entry->reg_type == XE_RTP_REG_MCR ?
xe_gt_mcr_unicast_read_any(gt, MCR_REG(reg)) :