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sample: rust: pci: use register! macro

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Convert the direct IO accesses to properly defined registers.

Tested-by: Zhi Wang <zhiw@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Link: https://patch.msgid.link/20260314-register-v9-9-86805b2f7e9d@nvidia.com
[ Fix up kernel import style. - Danilo ]
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
This commit is contained in:
Alexandre Courbot 2026-03-14 10:06:19 +09:00 committed by Danilo Krummrich
parent 9a52a8f5ed
commit 79cf41692a
1 changed files with 68 additions and 22 deletions
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90
samples/rust/rust_driver_pci.rs
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@ -5,30 +5,63 @@
//! To make this driver probe, QEMU must be run with `-device pci-testdev`.
use kernel::{
device::Bound,
device::Core,
device::{
Bound,
Core, //
},
devres::Devres,
io::Io,
io::{
register,
register::Array,
Io, //
},
num::Bounded,
pci,
prelude::*,
sync::aref::ARef, //
};
struct Regs;
mod regs {
use super::*;
impl Regs {
const TEST: usize = 0x0;
const OFFSET: usize = 0x4;
const DATA: usize = 0x8;
const COUNT: usize = 0xC;
const END: usize = 0x10;
register! {
pub(super) TEST(u8) @ 0x0 {
7:0 index => TestIndex;
}
pub(super) OFFSET(u32) @ 0x4 {
31:0 offset;
}
pub(super) DATA(u8) @ 0x8 {
7:0 data;
}
pub(super) COUNT(u32) @ 0xC {
31:0 count;
}
}
pub(super) const END: usize = 0x10;
}
type Bar0 = pci::Bar<{ Regs::END }>;
type Bar0 = pci::Bar<{ regs::END }>;
#[derive(Copy, Clone, Debug)]
struct TestIndex(u8);
impl From<Bounded<u8, 8>> for TestIndex {
fn from(value: Bounded<u8, 8>) -> Self {
Self(value.into())
}
}
impl From<TestIndex> for Bounded<u8, 8> {
fn from(value: TestIndex) -> Self {
value.0.into()
}
}
impl TestIndex {
const NO_EVENTFD: Self = Self(0);
}
@ -54,40 +87,53 @@ struct SampleDriver {
impl SampleDriver {
fn testdev(index: &TestIndex, bar: &Bar0) -> Result<u32> {
// Select the test.
bar.write8(index.0, Regs::TEST);
bar.write_reg(regs::TEST::zeroed().with_index(*index));
let offset = bar.read32(Regs::OFFSET) as usize;
let data = bar.read8(Regs::DATA);
let offset = bar.read(regs::OFFSET).into_raw() as usize;
let data = bar.read(regs::DATA).into();
// Write `data` to `offset` to increase `count` by one.
//
// Note that we need `try_write8`, since `offset` can't be checked at compile-time.
bar.try_write8(data, offset)?;
Ok(bar.read32(Regs::COUNT))
Ok(bar.read(regs::COUNT).into())
}
fn config_space(pdev: &pci::Device<Bound>) {
let config = pdev.config_space();
// TODO: use the register!() macro for defining PCI configuration space registers once it
// has been move out of nova-core.
// Some PCI configuration space registers.
register! {
VENDOR_ID(u16) @ 0x0 {
15:0 vendor_id;
}
REVISION_ID(u8) @ 0x8 {
7:0 revision_id;
}
BAR(u32)[6] @ 0x10 {
31:0 value;
}
}
dev_info!(
pdev,
"pci-testdev config space read8 rev ID: {:x}\n",
config.read8(0x8)
config.read(REVISION_ID).revision_id()
);
dev_info!(
pdev,
"pci-testdev config space read16 vendor ID: {:x}\n",
config.read16(0)
config.read(VENDOR_ID).vendor_id()
);
dev_info!(
pdev,
"pci-testdev config space read32 BAR 0: {:x}\n",
config.read32(0x10)
config.read(BAR::at(0)).value()
);
}
}
@ -111,7 +157,7 @@ fn probe(pdev: &pci::Device<Core>, info: &Self::IdInfo) -> impl PinInit<Self, Er
pdev.set_master();
Ok(try_pin_init!(Self {
bar <- pdev.iomap_region_sized::<{ Regs::END }>(0, c"rust_driver_pci"),
bar <- pdev.iomap_region_sized::<{ regs::END }>(0, c"rust_driver_pci"),
index: *info,
_: {
let bar = bar.access(pdev.as_ref())?;
@ -131,7 +177,7 @@ fn probe(pdev: &pci::Device<Core>, info: &Self::IdInfo) -> impl PinInit<Self, Er
fn unbind(pdev: &pci::Device<Core>, this: Pin<&Self>) {
if let Ok(bar) = this.bar.access(pdev.as_ref()) {
// Reset pci-testdev by writing a new test index.
bar.write8(this.index.0, Regs::TEST);
bar.write_reg(regs::TEST::zeroed().with_index(this.index));
}
}
}