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clk: samsung: exynos850: Add TMU clock
Add TMU PCLK clock in CMU_PERI unit. It acts simultaneously as an interface clock (to access TMU registers) and an operating clock which makes TMU IP-core functional. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240723163311.28654-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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@ -28,7 +28,7 @@
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#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
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#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
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#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
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#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
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#define CLKS_NR_PERI (CLK_GOUT_BUSIF_TMU_PCLK + 1)
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#define CLKS_NR_CORE (CLK_GOUT_SPDMA_CORE_ACLK + 1)
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#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
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@ -1921,6 +1921,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
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#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
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#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
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#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
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#define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK 0x2018
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#define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
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#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
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#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
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@ -1957,6 +1958,7 @@ static const unsigned long peri_clk_regs[] __initconst = {
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CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
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CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
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CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
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CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK,
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CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
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CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
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CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
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@ -2068,6 +2070,9 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
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GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
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"mout_peri_bus_user",
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CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_GOUT_BUSIF_TMU_PCLK, "gout_busif_tmu_pclk",
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"mout_peri_bus_user",
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CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, 21, 0, 0),
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};
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static const struct samsung_cmu_info peri_cmu_info __initconst = {
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