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clk: renesas: rzg2l: Drop always-false check in rzg3s_cpg_pll_clk_recalc_rate()

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Drop the unwanted check in rzg3s_cpg_pll_clk_recalc_rate() as the
function is SoC-specific.

Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260326110648.29389-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2026-03-26 11:06:35 +00:00 committed by Geert Uytterhoeven
parent 254f49634e
commit 79b5d6970b
1 changed files with 0 additions and 3 deletions
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3
drivers/clk/renesas/rzg2l-cpg.c
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@ -1107,9 +1107,6 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
u32 nir, nfr, mr, pr, val, setting;
u64 rate;
if (pll_clk->type != CLK_TYPE_G3S_PLL)
return parent_rate;
setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);
if (setting) {
val = readl(priv->base + setting);