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rtw89: support hardware generate security header
The newer chip will generate security header itself, so don't set IEEE80211_KEY_FLAG_GENERATE_IV in this kind of chip. But, it needs to fill key_index, PN and 802.11 header length to TX descriptor, and then hardware uses these to generate security header. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220318023214.32411-11-pkshih@realtek.com
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parent
f59acdde51
commit
79a6c9a4f3
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@ -320,6 +320,7 @@ int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev,
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struct ieee80211_sta *sta,
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struct ieee80211_key_conf *key)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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u8 hw_key_type;
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bool ext_key = false;
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int ret;
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@ -353,7 +354,8 @@ int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev,
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return -EOPNOTSUPP;
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}
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key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
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if (!chip->hw_sec_hdr)
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key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
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ret = rtw89_cam_sec_key_install(rtwdev, vif, sta, key, hw_key_type,
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ext_key);
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@ -435,6 +435,7 @@ static void
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rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
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struct rtw89_core_tx_request *tx_req)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct ieee80211_vif *vif = tx_req->vif;
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struct ieee80211_sta *sta = tx_req->sta;
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struct ieee80211_tx_info *info;
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@ -446,6 +447,7 @@ rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
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struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
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struct sk_buff *skb = tx_req->skb;
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u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
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u64 pn64;
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if (!vif) {
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rtw89_warn(rtwdev, "cannot set sec key without vif\n");
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@ -491,8 +493,21 @@ rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
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}
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desc_info->sec_en = true;
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desc_info->sec_keyid = key->keyidx;
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desc_info->sec_type = sec_type;
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desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
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if (!chip->hw_sec_hdr)
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return;
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pn64 = atomic64_inc_return(&key->tx_pn);
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desc_info->sec_seq[0] = pn64;
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desc_info->sec_seq[1] = pn64 >> 8;
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desc_info->sec_seq[2] = pn64 >> 16;
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desc_info->sec_seq[3] = pn64 >> 24;
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desc_info->sec_seq[4] = pn64 >> 32;
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desc_info->sec_seq[5] = pn64 >> 40;
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desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
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}
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static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
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@ -755,6 +770,17 @@ rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
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return PACKET_MAX;
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}
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static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
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struct rtw89_tx_desc_info *desc_info,
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struct sk_buff *skb)
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{
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struct ieee80211_hdr *hdr = (void *)skb->data;
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__le16 fc = hdr->frame_control;
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desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
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desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
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}
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static void
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rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
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struct rtw89_core_tx_request *tx_req)
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@ -806,6 +832,7 @@ rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
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rtw89_core_tx_update_data_info(rtwdev, tx_req);
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pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
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rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
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rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
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break;
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case RTW89_CORE_TX_TYPE_FWCMD:
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rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
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@ -912,6 +939,7 @@ static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
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static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
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{
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u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
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FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
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FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
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return cpu_to_le32(dword);
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@ -936,6 +964,24 @@ static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
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return cpu_to_le32(dword);
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}
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static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
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{
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u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
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FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
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return cpu_to_le32(dword);
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}
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static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
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{
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u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
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FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
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FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
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FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
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return cpu_to_le32(dword);
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}
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static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
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{
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u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
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@ -1032,6 +1078,10 @@ void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
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txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
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txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
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txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
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if (desc_info->sec_en) {
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txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
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txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
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}
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txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
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if (!desc_info->en_wd_info)
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@ -733,8 +733,10 @@ struct rtw89_tx_desc_info {
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u8 ampdu_num;
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bool sec_en;
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u8 addr_info_nr;
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u8 sec_keyid;
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u8 sec_type;
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u8 sec_cam_idx;
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u8 sec_seq[6];
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u16 data_rate;
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u16 data_retry_lowest_rate;
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bool fw_dl;
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@ -2302,6 +2304,7 @@ struct rtw89_chip_info {
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u32 rf_base_addr[2];
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u8 support_bands;
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bool support_bw160;
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bool hw_sec_hdr;
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u8 rf_path_num;
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u8 tx_nss;
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u8 rx_nss;
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@ -2066,6 +2066,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
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.support_bands = BIT(NL80211_BAND_2GHZ) |
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BIT(NL80211_BAND_5GHZ),
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.support_bw160 = false,
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.hw_sec_hdr = false,
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.rf_path_num = 2,
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.tx_nss = 2,
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.rx_nss = 2,
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@ -508,6 +508,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
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.rf_base_addr = {0xe000, 0xf000},
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.pwr_on_seq = NULL,
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.pwr_off_seq = NULL,
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.hw_sec_hdr = true,
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.sec_ctrl_efuse_size = 4,
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.physical_efuse_size = 1216,
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.logical_efuse_size = 2048,
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@ -38,6 +38,7 @@
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/* TX WD BODY DWORD 1 */
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#define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
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#define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
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#define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4)
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#define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
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/* TX WD BODY DWORD 2 */
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@ -52,8 +53,14 @@
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#define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0)
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/* TX WD BODY DWORD 4 */
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#define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
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#define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16)
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/* TX WD BODY DWORD 5 */
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#define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
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#define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16)
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#define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8)
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#define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)
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/* TX WD BODY DWORD 6 (V1) */
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