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drm/amd/display: Modify HPO pixel clock programming to support DPM
Need to select DTBCLK and DPREFCLK as DTBCLK_p source according to hardware guidance. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1082,11 +1082,11 @@ static bool dcn401_program_pix_clk(
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// all but TMDS gets Driver to program DP_DTO without calling VBIOS Command table
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if (!dc_is_tmds_signal(pix_clk_params->signal_type)) {
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long long ref_dtbclk_khz = clock_source->ctx->dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(clock_source->ctx->dc->clk_mgr);
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long long dprefclk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
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long long dtbclk_p_src_clk_khz;
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/* if signal is DP132B128B dtbclk_p_src is DTBCLK else DPREFCLK */
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dtbclk_p_src_clk_khz = encoding == DP_128b_132b_ENCODING ? ref_dtbclk_khz : dprefclk_khz;
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dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
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dto_params.clk_src = DPREFCLK;
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if (e) {
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dto_params.pixclk_hz = e->target_pixel_rate_khz * e->mult_factor;
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dto_params.refclk_hz = dtbclk_p_src_clk_khz * e->div_factor;
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