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Update TI clksel clocks to use reg

Browse Source 
Updates for TI clksel clocks to use the standard reg property instead of
 the non-standard ti,bit-shift legacy property.
 
 There are still lots of TI composite clock related devicetree warnings for
 missing bindings, and overlapping reg properties. We have grouped some of
 the TI composite clocks under the clksel clock node, but did not consider
 the reg property issue. Let's update the existing users before we continue
 grouping more of the composite clocks.
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Merge tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/late

Update TI clksel clocks to use reg

Updates for TI clksel clocks to use the standard reg property instead of
the non-standard ti,bit-shift legacy property.

There are still lots of TI composite clock related devicetree warnings for
missing bindings, and overlapping reg properties. We have grouped some of
the TI composite clocks under the clksel clock node, but did not consider
the reg property issue. Let's update the existing users before we continue
grouping more of the composite clocks.

* tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
  ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
  clk: ti: Improve clksel clock bit parsing for reg property
  clk: ti: Handle possible address in the node name

Link: https://lore.kernel.org/r/pull-1709102378-94138@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-04 17:36:56 +01:00
commit 794f877064
16 changed files with 491 additions and 405 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi
View File

@ -108,30 +108,31 @@ clock@664 {
compatible = "ti,clksel";
reg = <0x664>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
ehrpwm0_tbclk: clock-ehrpwm0-tbclk@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "ehrpwm0_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
};
ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
ehrpwm1_tbclk: clock-ehrpwm1-tbclk@1 {
reg = <1>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "ehrpwm1_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
};
ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
ehrpwm2_tbclk: clock-ehrpwm2-tbclk@2 {
reg = <2>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "ehrpwm2_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
};
};
};
@ -566,17 +567,19 @@ clock@52c {
compatible = "ti,clksel";
reg = <0x52c>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 {
reg = <1>;
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "gfx_fclk_clksel_ck";
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
ti,bit-shift = <1>;
};
gfx_fck_div_ck: clock-gfx-fck-div {
gfx_fck_div_ck: clock-gfx-fck-div@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "gfx_fck_div_ck";
@ -589,30 +592,32 @@ clock@700 {
compatible = "ti,clksel";
reg = <0x700>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
sysclkout_pre_ck: clock-sysclkout-pre {
sysclkout_pre_ck: clock-sysclkout-pre@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "sysclkout_pre_ck";
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
};
clkout2_div_ck: clock-clkout2-div {
clkout2_div_ck: clock-clkout2-div@3 {
reg = <3>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "clkout2_div_ck";
clocks = <&sysclkout_pre_ck>;
ti,bit-shift = <3>;
ti,max-div = <8>;
};
clkout2_ck: clock-clkout2 {
clkout2_ck: clock-clkout2@7 {
reg = <7>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "clkout2_ck";
clocks = <&clkout2_div_ck>;
ti,bit-shift = <7>;
};
};
};

18
arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi
View File

@ -66,22 +66,23 @@ clock@a10 {
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
ipss_ick: clock-ipss-ick {
ipss_ick: clock-ipss-ick@4 {
reg = <4>;
#clock-cells = <0>;
compatible = "ti,am35xx-interface-clock";
clock-output-names = "ipss_ick";
clocks = <&core_l3_ick>;
ti,bit-shift = <4>;
};
uart4_ick_am35xx: clock-uart4-ick-am35xx {
uart4_ick_am35xx: clock-uart4-ick-am35xx@23 {
reg = <23>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "uart4_ick_am35xx";
clocks = <&core_l4_ick>;
ti,bit-shift = <23>;
};
};
@ -101,14 +102,15 @@ clock@a00 {
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
uart4_fck_am35xx: clock-uart4-fck-am35xx {
uart4_fck_am35xx: clock-uart4-fck-am35xx@23 {
reg = <23>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "uart4_fck_am35xx";
clocks = <&core_48m_fck>;
ti,bit-shift = <23>;
};
};
};

52
arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi
View File

@ -50,30 +50,31 @@ clock@a00 {
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
d2d_26m_fck: clock-d2d-26m-fck {
d2d_26m_fck: clock-d2d-26m-fck@3 {
reg = <3>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "d2d_26m_fck";
clocks = <&sys_ck>;
ti,bit-shift = <3>;
};
fshostusb_fck: clock-fshostusb-fck {
fshostusb_fck: clock-fshostusb-fck@5 {
reg = <5>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "fshostusb_fck";
clocks = <&core_48m_fck>;
ti,bit-shift = <5>;
};
ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clock-output-names = "ssi_ssr_gate_fck_3430es1";
clocks = <&corex2_fck>;
ti,bit-shift = <0>;
};
};
@ -81,23 +82,24 @@ clock@a40 {
compatible = "ti,clksel";
reg = <0xa40>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 {
reg = <8>;
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clock-output-names = "ssi_ssr_div_fck_3430es1";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
usb_l4_div_ick: clock-usb-l4-div-ick {
usb_l4_div_ick: clock-usb-l4-div-ick@4 {
reg = <4>;
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clock-output-names = "usb_l4_div_ick";
clocks = <&l4_ick>;
ti,bit-shift = <4>;
ti,max-div = <1>;
ti,index-starts-at-one;
};
@ -121,38 +123,39 @@ clock@a10 {
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 {
hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 {
reg = <4>;
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clock-output-names = "hsotgusb_ick_3430es1";
clocks = <&core_l3_ick>;
ti,bit-shift = <4>;
};
fac_ick: clock-fac-ick {
fac_ick: clock-fac-ick@8 {
reg = <8>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "fac_ick";
clocks = <&core_l4_ick>;
ti,bit-shift = <8>;
};
ssi_ick: clock-ssi-ick-3430es1 {
ssi_ick: clock-ssi-ick-3430es1@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clock-output-names = "ssi_ick_3430es1";
clocks = <&ssi_l4_ick>;
ti,bit-shift = <0>;
};
usb_l4_gate_ick: clock-usb-l4-gate-ick {
usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {
reg = <5>;
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clock-output-names = "usb_l4_gate_ick";
clocks = <&l4_ick>;
ti,bit-shift = <5>;
};
};
@ -174,14 +177,15 @@ clock@e00 {
compatible = "ti,clksel";
reg = <0xe00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "dss1_alwon_fck_3430es1";
clocks = <&dpll4_m4x2_ck>;
ti,bit-shift = <0>;
ti,set-rate-parent;
};
};

86
arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi
View File

@ -17,46 +17,47 @@ clock@a14 {
compatible = "ti,clksel";
reg = <0xa14>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
aes1_ick: clock-aes1-ick {
aes1_ick: clock-aes1-ick@3 {
reg = <3>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "aes1_ick";
clocks = <&security_l4_ick2>;
ti,bit-shift = <3>;
};
rng_ick: clock-rng-ick {
rng_ick: clock-rng-ick@2 {
reg = <2>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "rng_ick";
clocks = <&security_l4_ick2>;
ti,bit-shift = <2>;
};
sha11_ick: clock-sha11-ick {
sha11_ick: clock-sha11-ick@1 {
reg = <1>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "sha11_ick";
clocks = <&security_l4_ick2>;
ti,bit-shift = <1>;
};
des1_ick: clock-des1-ick {
des1_ick: clock-des1-ick@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "des1_ick";
clocks = <&security_l4_ick2>;
ti,bit-shift = <0>;
};
pka_ick: clock-pka-ick {
pka_ick: clock-pka-ick@4 {
reg = <4>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "pka_ick";
clocks = <&security_l3_ick>;
ti,bit-shift = <4>;
};
};
@ -65,23 +66,24 @@ clock@f00 {
compatible = "ti,clksel";
reg = <0xf00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
cam_mclk: clock-cam-mclk {
cam_mclk: clock-cam-mclk@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "cam_mclk";
clocks = <&dpll4_m5x2_ck>;
ti,bit-shift = <0>;
ti,set-rate-parent;
};
csi2_96m_fck: clock-csi2-96m-fck {
csi2_96m_fck: clock-csi2-96m-fck@1 {
reg = <1>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "csi2_96m_fck";
clocks = <&core_96m_fck>;
ti,bit-shift = <1>;
};
};
@ -105,46 +107,47 @@ clock@a10 {
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
icr_ick: clock-icr-ick {
icr_ick: clock-icr-ick@29 {
reg = <29>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "icr_ick";
clocks = <&core_l4_ick>;
ti,bit-shift = <29>;
};
des2_ick: clock-des2-ick {
des2_ick: clock-des2-ick@26 {
reg = <26>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "des2_ick";
clocks = <&core_l4_ick>;
ti,bit-shift = <26>;
};
mspro_ick: clock-mspro-ick {
mspro_ick: clock-mspro-ick@23 {
reg = <23>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mspro_ick";
clocks = <&core_l4_ick>;
ti,bit-shift = <23>;
};
mailboxes_ick: clock-mailboxes-ick {
mailboxes_ick: clock-mailboxes-ick@7 {
reg = <7>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mailboxes_ick";
clocks = <&core_l4_ick>;
ti,bit-shift = <7>;
};
sad2d_ick: clock-sad2d-ick {
sad2d_ick: clock-sad2d-ick@3 {
reg = <3>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "sad2d_ick";
clocks = <&l3_ick>;
ti,bit-shift = <3>;
};
};
@ -160,22 +163,23 @@ clock@c00 {
compatible = "ti,clksel";
reg = <0xc00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
sr1_fck: clock-sr1-fck {
sr1_fck: clock-sr1-fck@6 {
reg = <6>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "sr1_fck";
clocks = <&sys_ck>;
ti,bit-shift = <6>;
};
sr2_fck: clock-sr2-fck {
sr2_fck: clock-sr2-fck@7 {
reg = <7>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "sr2_fck";
clocks = <&sys_ck>;
ti,bit-shift = <7>;
};
};
@ -228,22 +232,23 @@ clock@a00 {
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
modem_fck: clock-modem-fck {
modem_fck: clock-modem-fck@31 {
reg = <31>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "modem_fck";
clocks = <&sys_ck>;
ti,bit-shift = <31>;
};
mspro_fck: clock-mspro-fck {
mspro_fck: clock-mspro-fck@23 {
reg = <23>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mspro_fck";
clocks = <&core_96m_fck>;
ti,bit-shift = <23>;
};
};
@ -252,14 +257,15 @@ clock@a18 {
compatible = "ti,clksel";
reg = <0xa18>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#ssize-cells = <0>;
mad2d_ick: clock-mad2d-ick {
mad2d_ick: clock-mad2d-ick@3 {
reg = <3>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mad2d_ick";
clocks = <&l3_ick>;
ti,bit-shift = <3>;
};
};

28
arch/arm/boot/dts/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
View File

@ -138,14 +138,15 @@ clock@a18 {
compatible = "ti,clksel";
reg = <0xa18>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
usbtll_ick: clock-usbtll-ick {
usbtll_ick: clock-usbtll-ick@2 {
reg = <2>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "usbtll_ick";
clocks = <&core_l4_ick>;
ti,bit-shift = <2>;
};
};
@ -153,14 +154,15 @@ clock@a10 {
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
mmchs3_ick: clock-mmchs3-ick {
mmchs3_ick: clock-mmchs3-ick@30 {
reg = <30>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mmchs3_ick";
clocks = <&core_l4_ick>;
ti,bit-shift = <30>;
};
};
@ -168,14 +170,15 @@ clock@a00 {
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
mmchs3_fck: clock-mmchs3-fck {
mmchs3_fck: clock-mmchs3-fck@30 {
reg = <30>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mmchs3_fck";
clocks = <&core_96m_fck>;
ti,bit-shift = <30>;
};
};
@ -183,14 +186,15 @@ clock@e00 {
compatible = "ti,clksel";
reg = <0xe00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clock-output-names = "dss1_alwon_fck_3430es2";
clocks = <&dpll4_m4x2_ck>;
ti,bit-shift = <0>;
ti,set-rate-parent;
};
};

7
arch/arm/boot/dts/ti/omap/omap36xx-clocks.dtsi
View File

@ -62,14 +62,15 @@ clock@1000 {
compatible = "ti,clksel";
reg = <0x1000>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
uart4_fck: clock-uart4-fck {
uart4_fck: clock-uart4-fck@18 {
reg = <18>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "uart4_fck";
clocks = <&per_48m_fck>;
ti,bit-shift = <18>;
};
};
};

46
arch/arm/boot/dts/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi
View File

@ -9,14 +9,15 @@ clock@a00 {
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clock-output-names = "ssi_ssr_gate_fck_3430es2";
clocks = <&corex2_fck>;
ti,bit-shift = <0>;
};
};
@ -24,14 +25,15 @@ clock@a40 {
compatible = "ti,clksel";
reg = <0xa40>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 {
reg = <8>;
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clock-output-names = "ssi_ssr_div_fck_3430es2";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
};
@ -54,22 +56,23 @@ clock@a10 {
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2@4 {
reg = <4>;
#clock-cells = <0>;
compatible = "ti,omap3-hsotgusb-interface-clock";
clock-output-names = "hsotgusb_ick_3430es2";
clocks = <&core_l3_ick>;
ti,bit-shift = <4>;
};
ssi_ick: clock-ssi-ick-3430es2 {
ssi_ick: clock-ssi-ick-3430es2@0 {
reg = <0>;
#clock-cells = <0>;
compatible = "ti,omap3-ssi-interface-clock";
clock-output-names = "ssi_ick_3430es2";
clocks = <&ssi_l4_ick>;
ti,bit-shift = <0>;
};
};
@ -85,14 +88,15 @@ clock@c00 {
compatible = "ti,clksel";
reg = <0xc00>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
usim_gate_fck: clock-usim-gate-fck {
usim_gate_fck: clock-usim-gate-fck@9 {
reg = <9>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "usim_gate_fck";
clocks = <&omap_96m_fck>;
ti,bit-shift = <9>;
};
};
@ -172,14 +176,15 @@ clock@c40 {
compatible = "ti,clksel";
reg = <0xc40>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
usim_mux_fck: clock-usim-mux-fck {
usim_mux_fck: clock-usim-mux-fck@3 {
reg = <3>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "usim_mux_fck";
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
ti,bit-shift = <3>;
ti,index-starts-at-one;
};
};
@ -194,14 +199,15 @@ clock@c10 {
compatible = "ti,clksel";
reg = <0xc10>;
#clock-cells = <2>;
#address-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
usim_ick: clock-usim-ick {
usim_ick: clock-usim-ick@9 {
reg = <9>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "usim_ick";
clocks = <&wkup_l4_ick>;
ti,bit-shift = <9>;
};
};
};

510
arch/arm/boot/dts/ti/omap/omap3xxx-clocks.dtsi
View File

File diff suppressed because it is too large Load Diff

11
drivers/clk/ti/apll.c
View File

@ -376,14 +376,9 @@ static void __init of_omap2_apll_setup(struct device_node *node)
}
clk_hw->fixed_rate = val;
if (of_property_read_u32(node, "ti,bit-shift", &val)) {
pr_err("%pOFn missing bit-shift\n", node);
goto cleanup;
}
clk_hw->enable_bit = val;
ad->enable_mask = 0x3 << val;
ad->autoidle_mask = 0x3 << val;
clk_hw->enable_bit = ti_clk_get_legacy_bit_shift(node);
ad->enable_mask = 0x3 << clk_hw->enable_bit;
ad->autoidle_mask = 0x3 << clk_hw->enable_bit;
if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
pr_err("%pOFn missing idlest-shift\n", node);

71
drivers/clk/ti/clk.c
View File

@ -7,6 +7,7 @@
* Tero Kristo <t-kristo@ti.com>
*/
#include <linux/cleanup.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
@ -15,6 +16,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/list.h>
#include <linux/minmax.h>
#include <linux/regmap.h>
#include <linux/string_helpers.h>
#include <linux/memblock.h>
@ -114,20 +116,26 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
/*
* Eventually we could standardize to using '_' for clk-*.c files to follow the
* TRM naming and leave out the tmp name here.
* TRM naming.
*/
static struct device_node *ti_find_clock_provider(struct device_node *from,
const char *name)
{
char *tmp __free(kfree) = NULL;
struct device_node *np;
bool found = false;
const char *n;
char *tmp;
char *p;
tmp = kstrdup_and_replace(name, '-', '_', GFP_KERNEL);
if (!tmp)
return NULL;
/* Ignore a possible address for the node name */
p = strchr(tmp, '@');
if (p)
*p = '\0';
/* Node named "clock" with "clock-output-names" */
for_each_of_allnodes_from(from, np) {
if (of_property_read_string_index(np, "clock-output-names",
@ -140,7 +148,6 @@ static struct device_node *ti_find_clock_provider(struct device_node *from,
break;
}
}
kfree(tmp);
if (found) {
of_node_put(from);
@ -148,7 +155,7 @@ static struct device_node *ti_find_clock_provider(struct device_node *from,
}
/* Fall back to using old node name base provider name */
return of_find_node_by_name(from, name);
return of_find_node_by_name(from, tmp);
}
/**
@ -301,8 +308,9 @@ int __init ti_clk_retry_init(struct device_node *node, void *user,
int ti_clk_get_reg_addr(struct device_node *node, int index,
struct clk_omap_reg *reg)
{
u32 val;
int i;
u32 clksel_addr, val;
bool is_clksel = false;
int i, err;
for (i = 0; i < CLK_MAX_MEMMAPS; i++) {
if (clocks_node_ptr[i] == node->parent)
@ -318,21 +326,62 @@ int ti_clk_get_reg_addr(struct device_node *node, int index,
reg->index = i;
if (of_property_read_u32_index(node, "reg", index, &val)) {
if (of_property_read_u32_index(node->parent, "reg",
index, &val)) {
pr_err("%pOFn or parent must have reg[%d]!\n",
node, index);
if (of_device_is_compatible(node->parent, "ti,clksel")) {
err = of_property_read_u32_index(node->parent, "reg", index, &clksel_addr);
if (err) {
pr_err("%pOFn parent clksel must have reg[%d]!\n", node, index);
return -EINVAL;
}
is_clksel = true;
}
err = of_property_read_u32_index(node, "reg", index, &val);
if (err && is_clksel) {
/* Legacy clksel with no reg and a possible ti,bit-shift property */
reg->offset = clksel_addr;
reg->bit = ti_clk_get_legacy_bit_shift(node);
reg->ptr = NULL;
return 0;
}
/* Updated clksel clock with a proper reg property */
if (is_clksel) {
reg->offset = clksel_addr;
reg->bit = val;
reg->ptr = NULL;
return 0;
}
/* Other clocks that may or may not have ti,bit-shift property */
reg->offset = val;
reg->bit = ti_clk_get_legacy_bit_shift(node);
reg->ptr = NULL;
return 0;
}
/**
* ti_clk_get_legacy_bit_shift - get bit shift for a clock register
* @node: device node for the clock
*
* Gets the clock register bit shift using the legacy ti,bit-shift
* property. Only needed for legacy clock, and can be eventually
* dropped once all the composite clocks use a clksel node with a
* proper reg property.
*/
int ti_clk_get_legacy_bit_shift(struct device_node *node)
{
int err;
u32 val;
err = of_property_read_u32(node, "ti,bit-shift", &val);
if (!err && in_range(val, 0, 32))
return val;
return 0;
}
void ti_clk_latch(struct clk_omap_reg *reg, s8 shift)
{
u32 latch;

1
drivers/clk/ti/clock.h
View File

@ -216,6 +216,7 @@ int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
int ti_clk_get_reg_addr(struct device_node *node, int index,
struct clk_omap_reg *reg);
int ti_clk_get_legacy_bit_shift(struct device_node *node);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
int ti_clk_retry_init(struct device_node *node, void *user,
ti_of_clk_init_cb_t func);

5
drivers/clk/ti/divider.c
View File

@ -477,10 +477,7 @@ static int __init ti_clk_divider_populate(struct device_node *node,
if (ret)
return ret;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
div->shift = val;
else
div->shift = 0;
div->shift = div->reg.bit;
if (!of_property_read_u32(node, "ti,latch-bit", &val))
div->latch = val;

9
drivers/clk/ti/gate.c
View File

@ -132,7 +132,6 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
struct clk_omap_reg reg;
const char *name;
u8 enable_bit = 0;
u32 val;
u32 flags = 0;
u8 clk_gate_flags = 0;
@ -140,8 +139,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
if (ti_clk_get_reg_addr(node, 0, &reg))
return;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
enable_bit = val;
enable_bit = reg.bit;
}
if (of_clk_get_parent_count(node) != 1) {
@ -170,7 +168,6 @@ _of_ti_composite_gate_clk_setup(struct device_node *node,
const struct clk_hw_omap_ops *hw_ops)
{
struct clk_hw_omap *gate;
u32 val = 0;
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
@ -179,9 +176,7 @@ _of_ti_composite_gate_clk_setup(struct device_node *node,
if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
goto cleanup;
of_property_read_u32(node, "ti,bit-shift", &val);
gate->enable_bit = val;
gate->enable_bit = gate->enable_reg.bit;
gate->ops = hw_ops;
if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))

4
drivers/clk/ti/interface.c
View File

@ -66,13 +66,11 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
struct clk_omap_reg reg;
u8 enable_bit = 0;
const char *name;
u32 val;
if (ti_clk_get_reg_addr(node, 0, &reg))
return;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
enable_bit = val;
enable_bit = reg.bit;
parent_name = of_clk_get_parent_name(node, 0);
if (!parent_name) {

6
drivers/clk/ti/mux.c
View File

@ -189,7 +189,7 @@ static void of_mux_clk_setup(struct device_node *node)
if (ti_clk_get_reg_addr(node, 0, &reg))
goto cleanup;
of_property_read_u32(node, "ti,bit-shift", &shift);
shift = reg.bit;
of_property_read_u32(node, "ti,latch-bit", &latch);
@ -252,7 +252,6 @@ static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
{
struct clk_omap_mux *mux;
unsigned int num_parents;
u32 val;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
@ -261,8 +260,7 @@ static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
if (ti_clk_get_reg_addr(node, 0, &mux->reg))
goto cleanup;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
mux->shift = val;
mux->shift = mux->reg.bit;
if (of_property_read_bool(node, "ti,index-starts-at-one"))
mux->flags |= CLK_MUX_INDEX_ONE;

3
include/linux/clk/ti.h
View File

@ -13,11 +13,14 @@
/**
* struct clk_omap_reg - OMAP register declaration
* @offset: offset from the master IP module base address
* @bit: register bit offset
* @index: index of the master IP module
* @flags: flags
*/
struct clk_omap_reg {
void __iomem *ptr;
u16 offset;
u8 bit;
u8 index;
u8 flags;
};