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arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity

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As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: b7e8f433a6 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/ca57409198477f7815e32a6a7467dcdc9b93dc4f.1613468366.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Sai Prakash Ranjan 2021-02-16 15:17:48 +05:30 committed by Bjorn Andersson
parent 93138ef5ac
commit 794d3e309e
1 changed files with 1 additions and 1 deletions
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2
arch/arm64/boot/dts/qcom/sm8350.dtsi
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@ -153,7 +153,7 @@ memory@80000000 {
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {