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dt-bindings: iio: Add PMIC5 GEN3 ADC support
Add definitions for ADC channels for PMIC5 GEN3 ADC driver. Add virtual channel definitions for PM5100, to be used by ADC clients for PMIC5 GEN3. Change-Id: I1180553c3ee697f994324c60ebfb4e996221108e Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
This commit is contained in:
Jishnu Prakash
David Collins
parent
9e5e68e310
commit
7945098ab3
83
include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h
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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H
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#define _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H
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#ifndef PM5100_SID
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#define PM5100_SID 0
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#endif
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/* ADC channels for PM5100_ADC for PMIC5 Gen3 */
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#define PM5100_ADC5_GEN3_OFFSET_REF (PM5100_SID << 8 | 0x0)
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#define PM5100_ADC5_GEN3_1P25VREF (PM5100_SID << 8 | 0x01)
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#define PM5100_ADC5_GEN3_VREF_VADC (PM5100_SID << 8 | 0x02)
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#define PM5100_ADC5_GEN3_DIE_TEMP (PM5100_SID << 8 | 0x03)
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#define PM5100_ADC5_GEN3_AMUX1_THM (PM5100_SID << 8 | 0x04)
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#define PM5100_ADC5_GEN3_AMUX2_THM (PM5100_SID << 8 | 0x05)
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#define PM5100_ADC5_GEN3_AMUX3_THM (PM5100_SID << 8 | 0x06)
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#define PM5100_ADC5_GEN3_AMUX4_THM (PM5100_SID << 8 | 0x07)
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#define PM5100_ADC5_GEN3_AMUX5_THM (PM5100_SID << 8 | 0x08)
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#define PM5100_ADC5_GEN3_AMUX6_THM (PM5100_SID << 8 | 0x09)
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#define PM5100_ADC5_GEN3_AMUX1_GPIO10 (PM5100_SID << 8 | 0x0a)
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#define PM5100_ADC5_GEN3_AMUX2_GPIO11 (PM5100_SID << 8 | 0x0b)
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#define PM5100_ADC5_GEN3_AMUX3_GPIO (PM5100_SID << 8 | 0x0c)
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#define PM5100_ADC5_GEN3_AMUX4_GPIO (PM5100_SID << 8 | 0x0d)
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#define PM5100_ADC5_GEN3_CHG_TEMP (PM5100_SID << 8 | 0x10)
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#define PM5100_ADC5_GEN3_USB_SNS_V_16 (PM5100_SID << 8 | 0x11)
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#define PM5100_ADC5_GEN3_VIN_DIV16_MUX (PM5100_SID << 8 | 0x12)
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#define PM5100_ADC5_GEN3_IIN_FB (PM5100_SID << 8 | 0x17)
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#define PM5100_ADC5_GEN3_ICHG_FB (PM5100_SID << 8 | 0xa1)
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/* 30k pull-up1 */
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#define PM5100_ADC5_GEN3_AMUX1_THM_30K_PU (PM5100_SID << 8 | 0x24)
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#define PM5100_ADC5_GEN3_AMUX2_THM_30K_PU (PM5100_SID << 8 | 0x25)
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#define PM5100_ADC5_GEN3_AMUX3_THM_30K_PU (PM5100_SID << 8 | 0x26)
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#define PM5100_ADC5_GEN3_AMUX4_THM_30K_PU (PM5100_SID << 8 | 0x27)
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#define PM5100_ADC5_GEN3_AMUX5_THM_30K_PU (PM5100_SID << 8 | 0x28)
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#define PM5100_ADC5_GEN3_AMUX6_THM_30K_PU (PM5100_SID << 8 | 0x29)
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#define PM5100_ADC5_GEN3_AMUX1_GPIO10_30K_PU (PM5100_SID << 8 | 0x2a)
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#define PM5100_ADC5_GEN3_AMUX2_GPIO11_30K_PU (PM5100_SID << 8 | 0x2b)
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#define PM5100_ADC5_GEN3_AMUX3_GPIO_30K_PU (PM5100_SID << 8 | 0x2c)
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#define PM5100_ADC5_GEN3_AMUX4_GPIO_30K_PU (PM5100_SID << 8 | 0x2d)
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#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b
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/* 100k pull-up2 */
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#define PM5100_ADC5_GEN3_AMUX1_THM_100K_PU (PM5100_SID << 8 | 0x44)
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#define PM5100_ADC5_GEN3_AMUX2_THM_100K_PU (PM5100_SID << 8 | 0x45)
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#define PM5100_ADC5_GEN3_AMUX3_THM_100K_PU (PM5100_SID << 8 | 0x46)
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#define PM5100_ADC5_GEN3_AMUX4_THM_100K_PU (PM5100_SID << 8 | 0x47)
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#define PM5100_ADC5_GEN3_AMUX5_THM_100K_PU (PM5100_SID << 8 | 0x48)
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#define PM5100_ADC5_GEN3_AMUX6_THM_100K_PU (PM5100_SID << 8 | 0x49)
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#define PM5100_ADC5_GEN3_AMUX1_GPIO10_100K_PU (PM5100_SID << 8 | 0x4a)
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#define PM5100_ADC5_GEN3_AMUX2_GPIO11_100K_PU (PM5100_SID << 8 | 0x4b)
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#define PM5100_ADC5_GEN3_AMUX3_GPIO_100K_PU (PM5100_SID << 8 | 0x4c)
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#define PM5100_ADC5_GEN3_AMUX4_GPIO_100K_PU (PM5100_SID << 8 | 0x4d)
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/* 400k pull-up3 */
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#define PM5100_ADC5_GEN3_AMUX1_THM_400K_PU (PM5100_SID << 8 | 0x64)
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#define PM5100_ADC5_GEN3_AMUX2_THM_400K_PU (PM5100_SID << 8 | 0x65)
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#define PM5100_ADC5_GEN3_AMUX3_THM_400K_PU (PM5100_SID << 8 | 0x66)
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#define PM5100_ADC5_GEN3_AMUX4_THM_400K_PU (PM5100_SID << 8 | 0x67)
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#define PM5100_ADC5_GEN3_AMUX5_THM_400K_PU (PM5100_SID << 8 | 0x68)
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#define PM5100_ADC5_GEN3_AMUX6_THM_400K_PU (PM5100_SID << 8 | 0x69)
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#define PM5100_ADC5_GEN3_AMUX1_GPIO10_400K_PU (PM5100_SID << 8 | 0x6a)
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#define PM5100_ADC5_GEN3_AMUX2_GPIO11_400K_PU (PM5100_SID << 8 | 0x6b)
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#define PM5100_ADC5_GEN3_AMUX3_GPIO_400K_PU (PM5100_SID << 8 | 0x6c)
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#define PM5100_ADC5_GEN3_AMUX4_GPIO_400K_PU (PM5100_SID << 8 | 0x6d)
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/* 1/3 Divider */
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#define PM5100_ADC5_GEN3_GPIO10_DIV3 (PM5100_SID << 8 | 0x8a)
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#define PM5100_ADC5_GEN3_GPIO11_DIV3 (PM5100_SID << 8 | 0x8b)
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#define PM5100_ADC5_GEN3_VPH_PWR (PM5100_SID << 8 | 0x8e)
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#define PM5100_ADC5_GEN3_VBAT_SNS_QBG (PM5100_SID << 8 | 0x8f)
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#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H */
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@ -300,6 +300,83 @@
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#define ADC7_SBUx 0x94
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#define ADC7_VBAT_2S_MID 0x96
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/* ADC channels for PMIC5 Gen3 */
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#define ADC5_GEN3_OFFSET_REF 0x00
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#define ADC5_GEN3_1P25VREF 0x01
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#define ADC5_GEN3_VREF_VADC 0x02
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#define ADC5_GEN3_DIE_TEMP 0x03
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#define ADC5_GEN3_AMUX1_THM 0x04
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#define ADC5_GEN3_AMUX2_THM 0x05
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#define ADC5_GEN3_AMUX3_THM 0x06
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#define ADC5_GEN3_AMUX4_THM 0x07
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#define ADC5_GEN3_AMUX5_THM 0x08
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#define ADC5_GEN3_AMUX6_THM 0x09
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#define ADC5_GEN3_AMUX1_GPIO 0x0a
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#define ADC5_GEN3_AMUX2_GPIO 0x0b
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#define ADC5_GEN3_AMUX3_GPIO 0x0c
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#define ADC5_GEN3_AMUX4_GPIO 0x0d
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#define ADC5_GEN3_CHG_TEMP 0x10
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#define ADC5_GEN3_USB_SNS_V_16 0x11
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#define ADC5_GEN3_VIN_DIV16_MUX 0x12
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#define ADC5_GEN3_VREF_BAT_THERM 0x15
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#define ADC5_GEN3_IIN_FB 0x17
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#define ADC5_GEN3_ICHG_SMB 0x18
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#define ADC5_GEN3_IIN_SMB 0x19
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#define ADC5_GEN3_ICHG_FB 0xa1
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/* 30k pull-up1 */
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#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24
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#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25
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#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26
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#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27
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#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28
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#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29
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#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a
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#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b
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#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c
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#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d
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/* 100k pull-up2 */
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#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44
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#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45
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#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46
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#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47
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#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48
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#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49
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#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a
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#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b
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#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c
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#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d
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/* 400k pull-up3 */
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#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
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#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
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#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
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#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
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#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
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#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
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#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
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#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
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#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
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#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
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/* 1/3 Divider */
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#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
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#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
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#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
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#define ADC5_GEN3_VPH_PWR 0x8e
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#define ADC5_GEN3_VBAT_SNS_QBG 0x8f
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#define ADC5_GEN3_VBAT_SNS_CHGR 0x94
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#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96
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#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d
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#define ADC5_OFFSET_EXT2 0xf8
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/* VADC scale function index */
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#define ADC_SCALE_DEFAULT 0
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#define ADC_SCALE_THERM_100K_PULLUP 1
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