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drm/xe: Consolidate workaround entries for Wa_14018471104
Wa_14018471104 applies to all graphics versions from 20.01 through 20.04 (inclusive). Consolidate the two RTP entries into a single range-based entry. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-11-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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@ -358,6 +358,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
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FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
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},
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{ XE_RTP_NAME("14018471104"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
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FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
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},
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/* TGL */
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@ -500,10 +505,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
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FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
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},
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{ XE_RTP_NAME("14018471104"),
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XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
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},
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/*
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* These two workarounds are the same, just applying to different
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* engines. Although Wa_18032095049 (for the RCS) isn't required on
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@ -545,11 +546,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
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FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
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},
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{ XE_RTP_NAME("14018471104"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
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FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
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},
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/*
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* Although this workaround isn't required for the RCS, disabling these
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* reports has no impact for our driver or the GuC, so we go ahead and
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