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x86/apic: Stop using 32-bit MSR interfaces

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The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.

Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://patch.msgid.link/20260629060526.3638272-19-jgross@suse.com
This commit is contained in:
Juergen Gross 2026-06-29 08:05:09 +02:00 committed by Ingo Molnar
parent 4967c466ca
commit 7920900e53
1 changed files with 20 additions and 19 deletions
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39
arch/x86/kernel/apic/apic.c
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@ -1191,11 +1191,11 @@ void disable_local_APIC(void)
* restore the disabled state.
*/
if (enabled_via_apicbase) {
unsigned int l, h;
struct msr val;
rdmsr(MSR_IA32_APICBASE, l, h);
l &= ~MSR_IA32_APICBASE_ENABLE;
wrmsr(MSR_IA32_APICBASE, l, h);
rdmsrq(MSR_IA32_APICBASE, val.q);
val.l &= ~MSR_IA32_APICBASE_ENABLE;
wrmsrq(MSR_IA32_APICBASE, val.q);
}
#endif
}
@ -1960,7 +1960,8 @@ static bool __init detect_init_APIC(void)
static bool __init apic_verify(unsigned long addr)
{
u32 features, h, l;
struct msr val;
u32 features;
/*
* The APIC feature bit should now be enabled
@ -1975,9 +1976,9 @@ static bool __init apic_verify(unsigned long addr)
/* The BIOS may have set up the APIC at some other address */
if (boot_cpu_data.x86 >= 6) {
rdmsr(MSR_IA32_APICBASE, l, h);
if (l & MSR_IA32_APICBASE_ENABLE)
addr = l & MSR_IA32_APICBASE_BASE;
rdmsrq(MSR_IA32_APICBASE, val.q);
if (val.l & MSR_IA32_APICBASE_ENABLE)
addr = val.l & MSR_IA32_APICBASE_BASE;
}
register_lapic_address(addr);
@ -1987,7 +1988,7 @@ static bool __init apic_verify(unsigned long addr)
bool __init apic_force_enable(unsigned long addr)
{
u32 h, l;
struct msr val;
if (apic_is_disabled)
return false;
@ -1998,12 +1999,12 @@ bool __init apic_force_enable(unsigned long addr)
* and AMD K7 (Model > 1) or later.
*/
if (boot_cpu_data.x86 >= 6) {
rdmsr(MSR_IA32_APICBASE, l, h);
if (!(l & MSR_IA32_APICBASE_ENABLE)) {
rdmsrq(MSR_IA32_APICBASE, val.q);
if (!(val.l & MSR_IA32_APICBASE_ENABLE)) {
pr_info("Local APIC disabled by BIOS -- reenabling.\n");
l &= ~MSR_IA32_APICBASE_BASE;
l |= MSR_IA32_APICBASE_ENABLE | addr;
wrmsr(MSR_IA32_APICBASE, l, h);
val.l &= ~MSR_IA32_APICBASE_BASE;
val.l |= MSR_IA32_APICBASE_ENABLE | addr;
wrmsrq(MSR_IA32_APICBASE, val.q);
enabled_via_apicbase = 1;
}
}
@ -2442,7 +2443,7 @@ static int lapic_suspend(void *data)
static void lapic_resume(void *data)
{
unsigned int l, h;
struct msr val;
unsigned long flags;
int maxlvt;
@ -2475,10 +2476,10 @@ static void lapic_resume(void *data)
* SMP! We'll need to do this as part of the CPU restore!
*/
if (boot_cpu_data.x86 >= 6) {
rdmsr(MSR_IA32_APICBASE, l, h);
l &= ~MSR_IA32_APICBASE_BASE;
l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
wrmsr(MSR_IA32_APICBASE, l, h);
rdmsrq(MSR_IA32_APICBASE, val.q);
val.l &= ~MSR_IA32_APICBASE_BASE;
val.l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
wrmsrq(MSR_IA32_APICBASE, val.q);
}
}