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drm/amdgpu: Fix GART page table s-bit

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For the new 2-level GART table, the last PDE0 points
to PTB. Since PTB is in vram and right now we are
runing under s=0 mode (vram is treated as FB carveout),
so the s bit of this PDE0 should be set to 0.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Oak Zeng 2021-01-22 21:51:39 -06:00 committed by Alex Deucher
parent f4ec3e5039
commit 79194dacb2
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
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@ -656,7 +656,7 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
* PTB who has more than 512 entries each
* pointing to a 4K system page
*/
flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM;
flags = AMDGPU_PTE_VALID;
flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED;
/* Requires gart_ptb_gpu_pa to be 4K aligned */
amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);