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platform/x86:intel/pmc: Move PMC Core related functions
Move functions that implements PMC Core feature from core_ssram.c to core.c. This patch is a preparation step to introduce a new SSRAM Telemetry driver for the SSRAM device. Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20250409191056.15434-2-xi.pardee@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
This commit is contained in:
Xi Pardee
Ilpo Järvinen
parent
88f67f2a99
commit
78a7491d5c
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@ -1345,6 +1345,173 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
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}
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}
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static u32 pmc_core_find_guid(struct pmc_info *list, const struct pmc_reg_map *map)
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{
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for (; list->map; ++list)
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if (list->map == map)
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return list->guid;
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return 0;
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}
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static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc)
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{
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struct telem_endpoint *ep;
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const u8 *lpm_indices;
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int num_maps, mode_offset = 0;
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int ret, mode;
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int lpm_size;
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u32 guid;
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lpm_indices = pmc->map->lpm_reg_index;
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num_maps = pmc->map->lpm_num_maps;
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lpm_size = LPM_MAX_NUM_MODES * num_maps;
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guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map);
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if (!guid)
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return -ENXIO;
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ep = pmt_telem_find_and_register_endpoint(pmcdev->ssram_pcidev, guid, 0);
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if (IS_ERR(ep)) {
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dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %ld",
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PTR_ERR(ep));
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return -EPROBE_DEFER;
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}
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pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev,
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lpm_size * sizeof(u32),
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GFP_KERNEL);
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if (!pmc->lpm_req_regs) {
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ret = -ENOMEM;
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goto unregister_ep;
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}
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/*
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* PMC Low Power Mode (LPM) table
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*
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* In telemetry space, the LPM table contains a 4 byte header followed
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* by 8 consecutive mode blocks (one for each LPM mode). Each block
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* has a 4 byte header followed by a set of registers that describe the
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* IP state requirements for the given mode. The IP mapping is platform
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* specific but the same for each block, making for easy analysis.
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* Platforms only use a subset of the space to track the requirements
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* for their IPs. Callers provide the requirement registers they use as
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* a list of indices. Each requirement register is associated with an
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* IP map that's maintained by the caller.
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*
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* Header
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* +----+----------------------------+----------------------------+
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* | 0 | REVISION | ENABLED MODES |
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* +----+--------------+-------------+-------------+--------------+
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*
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* Low Power Mode 0 Block
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* +----+--------------+-------------+-------------+--------------+
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* | 1 | SUB ID | SIZE | MAJOR | MINOR |
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* +----+--------------+-------------+-------------+--------------+
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* | 2 | LPM0 Requirements 0 |
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* +----+---------------------------------------------------------+
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* | | ... |
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* +----+---------------------------------------------------------+
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* | 29 | LPM0 Requirements 27 |
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* +----+---------------------------------------------------------+
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*
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* ...
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*
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* Low Power Mode 7 Block
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* +----+--------------+-------------+-------------+--------------+
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* | | SUB ID | SIZE | MAJOR | MINOR |
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* +----+--------------+-------------+-------------+--------------+
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* | 60 | LPM7 Requirements 0 |
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* +----+---------------------------------------------------------+
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* | | ... |
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* +----+---------------------------------------------------------+
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* | 87 | LPM7 Requirements 27 |
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* +----+---------------------------------------------------------+
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*
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*/
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mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET;
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pmc_for_each_mode(mode, pmcdev) {
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u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps);
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int m;
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for (m = 0; m < num_maps; m++) {
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u8 sample_id = lpm_indices[m] + mode_offset;
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ret = pmt_telem_read32(ep, sample_id, req_offset, 1);
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if (ret) {
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dev_err(&pmcdev->pdev->dev,
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"couldn't read Low Power Mode requirements: %d\n", ret);
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devm_kfree(&pmcdev->pdev->dev, pmc->lpm_req_regs);
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goto unregister_ep;
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}
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++req_offset;
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}
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mode_offset += LPM_REG_COUNT + LPM_MODE_OFFSET;
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}
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unregister_ep:
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pmt_telem_unregister_endpoint(ep);
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return ret;
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}
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static int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev)
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{
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int ret, i;
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if (!pmcdev->ssram_pcidev)
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return -ENODEV;
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for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
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if (!pmcdev->pmcs[i])
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continue;
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ret = pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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const struct pmc_reg_map *pmc_core_find_regmap(struct pmc_info *list, u16 devid)
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{
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for (; list->map; ++list)
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if (devid == list->devid)
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return list->map;
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return NULL;
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}
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int pmc_core_pmc_add(struct pmc_dev *pmcdev, u64 pwrm_base,
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const struct pmc_reg_map *reg_map, int pmc_index)
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{
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struct pmc *pmc = pmcdev->pmcs[pmc_index];
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if (!pwrm_base)
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return -ENODEV;
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/* Memory for primary PMC has been allocated in core.c */
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if (!pmc) {
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pmc = devm_kzalloc(&pmcdev->pdev->dev, sizeof(*pmc), GFP_KERNEL);
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if (!pmc)
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return -ENOMEM;
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}
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pmc->map = reg_map;
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pmc->base_addr = pwrm_base;
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pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length);
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if (!pmc->regbase) {
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devm_kfree(&pmcdev->pdev->dev, pmc);
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return -ENOMEM;
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}
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pmcdev->pmcs[pmc_index] = pmc;
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return 0;
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}
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/*
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* When supported, ssram init is used to achieve all available PMCs.
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* If ssram init fails, this function uses legacy method to at least get the
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@ -1719,5 +1886,6 @@ static struct platform_driver pmc_core_driver = {
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module_platform_driver(pmc_core_driver);
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MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Intel PMC Core Driver");
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@ -24,6 +24,11 @@ struct telem_endpoint;
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#define MAX_NUM_PMC 3
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#define S0IX_BLK_SIZE 4
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/* PCH query */
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#define LPM_HEADER_OFFSET 1
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#define LPM_REG_COUNT 28
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#define LPM_MODE_OFFSET 1
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/* Sunrise Point Power Management Controller PCI Device ID */
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#define SPT_PMC_PCI_DEVICE_ID 0x9d21
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#define SPT_PMC_BASE_ADDR_OFFSET 0x48
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@ -485,7 +490,6 @@ extern const struct pmc_reg_map mtl_socm_reg_map;
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extern const struct pmc_reg_map mtl_ioep_reg_map;
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void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
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int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev);
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int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore);
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int pmc_core_resume_common(struct pmc_dev *pmcdev);
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@ -497,6 +501,9 @@ void pmc_core_set_device_d3(unsigned int device);
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int pmc_core_ssram_init(struct pmc_dev *pmcdev, int func);
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int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
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const struct pmc_reg_map *pmc_core_find_regmap(struct pmc_info *list, u16 devid);
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int pmc_core_pmc_add(struct pmc_dev *pmcdev, u64 pwrm_base,
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const struct pmc_reg_map *reg_map, int pmc_index);
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extern struct pmc_dev_info spt_pmc_dev;
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extern struct pmc_dev_info cnp_pmc_dev;
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@ -14,7 +14,6 @@
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include "core.h"
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#include "../pmt/telemetry.h"
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#define SSRAM_HDR_SIZE 0x100
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#define SSRAM_PWRM_OFFSET 0x14
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@ -24,142 +23,8 @@
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#define SSRAM_IOE_OFFSET 0x68
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#define SSRAM_DEVID_OFFSET 0x70
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/* PCH query */
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#define LPM_HEADER_OFFSET 1
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#define LPM_REG_COUNT 28
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#define LPM_MODE_OFFSET 1
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DEFINE_FREE(pmc_core_iounmap, void __iomem *, if (_T) iounmap(_T))
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static u32 pmc_core_find_guid(struct pmc_info *list, const struct pmc_reg_map *map)
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{
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for (; list->map; ++list)
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if (list->map == map)
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return list->guid;
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return 0;
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}
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static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc)
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{
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struct telem_endpoint *ep;
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const u8 *lpm_indices;
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int num_maps, mode_offset = 0;
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int ret, mode;
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int lpm_size;
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u32 guid;
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lpm_indices = pmc->map->lpm_reg_index;
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num_maps = pmc->map->lpm_num_maps;
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lpm_size = LPM_MAX_NUM_MODES * num_maps;
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guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map);
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if (!guid)
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return -ENXIO;
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ep = pmt_telem_find_and_register_endpoint(pmcdev->ssram_pcidev, guid, 0);
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if (IS_ERR(ep)) {
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dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %ld",
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PTR_ERR(ep));
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return -EPROBE_DEFER;
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}
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pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev,
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lpm_size * sizeof(u32),
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GFP_KERNEL);
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if (!pmc->lpm_req_regs) {
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ret = -ENOMEM;
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goto unregister_ep;
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}
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/*
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* PMC Low Power Mode (LPM) table
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*
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* In telemetry space, the LPM table contains a 4 byte header followed
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* by 8 consecutive mode blocks (one for each LPM mode). Each block
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* has a 4 byte header followed by a set of registers that describe the
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* IP state requirements for the given mode. The IP mapping is platform
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* specific but the same for each block, making for easy analysis.
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* Platforms only use a subset of the space to track the requirements
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* for their IPs. Callers provide the requirement registers they use as
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* a list of indices. Each requirement register is associated with an
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* IP map that's maintained by the caller.
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*
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* Header
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* +----+----------------------------+----------------------------+
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* | 0 | REVISION | ENABLED MODES |
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* +----+--------------+-------------+-------------+--------------+
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*
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* Low Power Mode 0 Block
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* +----+--------------+-------------+-------------+--------------+
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* | 1 | SUB ID | SIZE | MAJOR | MINOR |
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* +----+--------------+-------------+-------------+--------------+
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* | 2 | LPM0 Requirements 0 |
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* +----+---------------------------------------------------------+
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* | | ... |
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* +----+---------------------------------------------------------+
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* | 29 | LPM0 Requirements 27 |
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* +----+---------------------------------------------------------+
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*
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* ...
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*
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* Low Power Mode 7 Block
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* +----+--------------+-------------+-------------+--------------+
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* | | SUB ID | SIZE | MAJOR | MINOR |
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* +----+--------------+-------------+-------------+--------------+
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* | 60 | LPM7 Requirements 0 |
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* +----+---------------------------------------------------------+
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* | | ... |
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* +----+---------------------------------------------------------+
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* | 87 | LPM7 Requirements 27 |
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* +----+---------------------------------------------------------+
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*
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*/
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mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET;
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pmc_for_each_mode(mode, pmcdev) {
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u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps);
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int m;
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for (m = 0; m < num_maps; m++) {
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u8 sample_id = lpm_indices[m] + mode_offset;
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ret = pmt_telem_read32(ep, sample_id, req_offset, 1);
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if (ret) {
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dev_err(&pmcdev->pdev->dev,
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"couldn't read Low Power Mode requirements: %d\n", ret);
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devm_kfree(&pmcdev->pdev->dev, pmc->lpm_req_regs);
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goto unregister_ep;
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}
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++req_offset;
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}
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mode_offset += LPM_REG_COUNT + LPM_MODE_OFFSET;
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}
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unregister_ep:
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pmt_telem_unregister_endpoint(ep);
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return ret;
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}
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int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev)
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{
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int ret, i;
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if (!pmcdev->ssram_pcidev)
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return -ENODEV;
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for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
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if (!pmcdev->pmcs[i])
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continue;
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ret = pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void
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pmc_add_pmt(struct pmc_dev *pmcdev, u64 ssram_base, void __iomem *ssram)
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{
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@ -203,50 +68,11 @@ pmc_add_pmt(struct pmc_dev *pmcdev, u64 ssram_base, void __iomem *ssram)
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intel_vsec_register(pcidev, &info);
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}
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static const struct pmc_reg_map *pmc_core_find_regmap(struct pmc_info *list, u16 devid)
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{
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for (; list->map; ++list)
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if (devid == list->devid)
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return list->map;
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return NULL;
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}
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static inline u64 get_base(void __iomem *addr, u32 offset)
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{
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return lo_hi_readq(addr + offset) & GENMASK_ULL(63, 3);
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}
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static int
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pmc_core_pmc_add(struct pmc_dev *pmcdev, u64 pwrm_base,
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const struct pmc_reg_map *reg_map, int pmc_index)
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{
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struct pmc *pmc = pmcdev->pmcs[pmc_index];
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if (!pwrm_base)
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return -ENODEV;
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/* Memory for primary PMC has been allocated in core.c */
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if (!pmc) {
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pmc = devm_kzalloc(&pmcdev->pdev->dev, sizeof(*pmc), GFP_KERNEL);
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if (!pmc)
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return -ENOMEM;
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}
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pmc->map = reg_map;
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pmc->base_addr = pwrm_base;
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pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length);
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if (!pmc->regbase) {
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devm_kfree(&pmcdev->pdev->dev, pmc);
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return -ENOMEM;
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}
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pmcdev->pmcs[pmc_index] = pmc;
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return 0;
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}
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static int
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pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, int pmc_idx, u32 offset)
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{
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@ -329,4 +155,3 @@ int pmc_core_ssram_init(struct pmc_dev *pmcdev, int func)
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return ret;
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}
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MODULE_IMPORT_NS("INTEL_VSEC");
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MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY");
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