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dt-bindings: dma: adi,axi-dmac: convert to yaml schema
Convert the AXI DMAC bindings from .txt to .yaml. Acked-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20241216-axi-dma-dt-yaml-v3-1-7b994710c43f@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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David Lechner
Vinod Koul
parent
9f6caa3978
commit
788726fcea
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Analog Devices AXI-DMAC DMA controller
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Required properties:
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- compatible: Must be "adi,axi-dmac-1.00.a".
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- reg: Specification for the controllers memory mapped register map.
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- interrupts: Specification for the controllers interrupt.
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- clocks: Phandle and specifier to the controllers AXI interface clock
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- #dma-cells: Must be 1.
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Required sub-nodes:
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- adi,channels: This sub-node must contain a sub-node for each DMA channel. For
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the channel sub-nodes the following bindings apply. They must match the
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configuration options of the peripheral as it was instantiated.
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Required properties for adi,channels sub-node:
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- #size-cells: Must be 0
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- #address-cells: Must be 1
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Required channel sub-node properties:
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- reg: Which channel this node refers to.
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- adi,source-bus-width,
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adi,destination-bus-width: Width of the source or destination bus in bits.
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- adi,source-bus-type,
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adi,destination-bus-type: Type of the source or destination bus. Must be one
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of the following:
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0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
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1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
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2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
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Deprecated optional channel properties:
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- adi,length-width: Width of the DMA transfer length register.
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- adi,cyclic: Must be set if the channel supports hardware cyclic DMA
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transfers.
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- adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
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DMA clients connected to the AXI-DMAC DMA controller must use the format
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described in the dma.txt file using a one-cell specifier. The value of the
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specifier refers to the DMA channel index.
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Example:
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dma: dma@7c420000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x7c420000 0x10000>;
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interrupts = <0 57 0>;
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clocks = <&clkc 16>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-width = <32>;
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adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
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adi,destination-bus-width = <64>;
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adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
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};
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};
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};
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139
Documentation/devicetree/bindings/dma/adi,axi-dmac.yaml
Normal file
139
Documentation/devicetree/bindings/dma/adi,axi-dmac.yaml
Normal file
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@ -0,0 +1,139 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/adi,axi-dmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices AXI-DMAC DMA controller
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description: |
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FPGA-based DMA controller designed for use with high-speed converter hardware.
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http://analogdevicesinc.github.io/hdl/library/axi_dmac/index.html
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maintainers:
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- Nuno Sa <nuno.sa@analog.com>
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additionalProperties: false
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properties:
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compatible:
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const: adi,axi-dmac-1.00.a
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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"#dma-cells":
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const: 1
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adi,channels:
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type: object
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description: This sub-node must contain a sub-node for each DMA channel.
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additionalProperties: false
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properties:
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"#size-cells":
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const: 0
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"#address-cells":
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const: 1
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patternProperties:
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"^dma-channel@[0-9a-f]+$":
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type: object
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description:
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DMA channel properties based on HDL compile-time configuration.
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additionalProperties: false
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properties:
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reg:
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maxItems: 1
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adi,source-bus-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Width of the source bus in bits.
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enum: [8, 16, 32, 64, 128]
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adi,destination-bus-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Width of the destination bus in bits.
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enum: [8, 16, 32, 64, 128]
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adi,source-bus-type:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Type of the source bus.
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0: Memory mapped AXI interface
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1: Streaming AXI interface
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2: FIFO interface
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enum: [0, 1, 2]
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adi,destination-bus-type:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Type of the destination bus (see adi,source-bus-type).
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enum: [0, 1, 2]
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adi,length-width:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Width of the DMA transfer length register.
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adi,cyclic:
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deprecated: true
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type: boolean
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description:
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Must be set if the channel supports hardware cyclic DMA transfers.
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adi,2d:
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deprecated: true
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type: boolean
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description:
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Must be set if the channel supports hardware 2D DMA transfers.
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required:
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- reg
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- adi,source-bus-width
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- adi,destination-bus-width
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- adi,source-bus-type
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- adi,destination-bus-type
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required:
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- "#size-cells"
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- "#address-cells"
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- "#dma-cells"
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- adi,channels
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examples:
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- |
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dma-controller@7c420000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x7c420000 0x10000>;
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interrupts = <0 57 0>;
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clocks = <&clkc 16>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-width = <32>;
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adi,source-bus-type = <0>; /* Memory mapped */
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adi,destination-bus-width = <64>;
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adi,destination-bus-type = <2>; /* FIFO */
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};
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};
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};
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