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media: qcom: camss: Add support for CSIPHY (v1.3.0)
Add support for CSIPHY (v1.3.0) found on lemans(sa8775p). This implementation is based on the titan 690 implementation. Co-developed-by: Wenmeng Liu <quic_wenmliu@quicinc.com> Signed-off-by: Wenmeng Liu <quic_wenmliu@quicinc.com> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
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@ -64,6 +64,85 @@ struct csiphy_lane_regs {
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u32 csiphy_param_type;
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};
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/* 5nm 2PH v 1.3.0 2p5Gbps 4 lane DPHY mode */
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static const struct
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csiphy_lane_regs lane_regs_sa8775p[] = {
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{0x0724, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x070C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x005C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0060, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x025C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0260, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x045C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0460, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x065C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0660, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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};
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/* GEN2 1.0 2PH */
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static const struct
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csiphy_lane_regs lane_regs_sdm845[] = {
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@ -834,6 +913,7 @@ static bool csiphy_is_gen2(u32 version)
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case CAMSS_8280XP:
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case CAMSS_845:
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case CAMSS_8550:
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case CAMSS_8775P:
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case CAMSS_X1E80100:
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ret = true;
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break;
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@ -937,6 +1017,10 @@ static int csiphy_init(struct csiphy_device *csiphy)
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regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
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regs->offset = 0x1000;
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break;
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case CAMSS_8775P:
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regs->lane_regs = &lane_regs_sa8775p[0];
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regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
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break;
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default:
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break;
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}
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@ -2617,6 +2617,77 @@ static const struct resources_icc icc_res_sm8550[] = {
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},
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};
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static const struct camss_subdev_resources csiphy_res_8775p[] = {
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/* CSIPHY0 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy_rx", "csiphy0", "csiphy0_timer"},
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.clock_rate = {
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{ 400000000 },
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{ 0 },
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{ 400000000 },
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},
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.reg = { "csiphy0" },
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.interrupt = { "csiphy0" },
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.csiphy = {
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.id = 0,
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY1 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy_rx", "csiphy1", "csiphy1_timer"},
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.clock_rate = {
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{ 400000000 },
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{ 0 },
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{ 400000000 },
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},
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.reg = { "csiphy1" },
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.interrupt = { "csiphy1" },
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.csiphy = {
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.id = 1,
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY2 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy_rx", "csiphy2", "csiphy2_timer"},
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.clock_rate = {
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{ 400000000 },
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{ 0 },
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{ 400000000 },
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},
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.reg = { "csiphy2" },
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.interrupt = { "csiphy2" },
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.csiphy = {
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.id = 2,
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY3 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy_rx", "csiphy3", "csiphy3_timer"},
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.clock_rate = {
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{ 400000000 },
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{ 0 },
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{ 400000000 },
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},
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.reg = { "csiphy3" },
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.interrupt = { "csiphy3" },
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.csiphy = {
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.id = 3,
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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};
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static const struct resources_icc icc_res_sa8775p[] = {
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{
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.name = "ahb",
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