diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c index e62ea054bc61..51348969bf49 100644 --- a/drivers/watchdog/npcm_wdt.c +++ b/drivers/watchdog/npcm_wdt.c @@ -7,14 +7,52 @@ #include #include #include +#include #include #include #include +#include #include #include #define NPCM_WTCR 0x1C +/* NPCM GCR module */ +#define NPCM_RESSR_OFFSET 0x6C +#define NPCM_INTCR2_OFFSET 0x60 +#define NPCM7XX_SCRPAD2_OFFSET 0x84 +#define NPCM8XX_SCRPAD10_OFFSET 0xE28 + +#define NPCM_PORST BIT(31) +#define NPCM_CORST BIT(30) +#define NPCM_WD0RST BIT(29) +#define NPCM_SWR1RST BIT(28) +#define NPCM_SWR2RST BIT(27) +#define NPCM_SWR3RST BIT(26) +#define NPCM_SWR4RST BIT(25) +#define NPCM_WD1RST BIT(24) +#define NPCM_WD2RST BIT(23) +#define NPCM_RST GENMASK(31, 23) +#define NPCM8XX_TIP_RESET BIT(25) /* Replaces SWRST4 on NPCM8xx */ + +/* Per-instance mapping of MMIO base address to its RESSR/INTCR2 reset bit. */ +struct npcm_wdt_rst_map { + phys_addr_t base; + u32 rst_bit; +}; + +struct npcm_wdt_status_map { + u32 rst_bit; + u32 wdiof_flag; +}; + +struct npcm_wdt_data { + const struct npcm_wdt_rst_map *rst_map; + unsigned int rst_map_size; + const struct npcm_wdt_status_map *status_map; + unsigned int status_map_size; +}; + #define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ #define NPCM_WTE BIT(7) /* Enable */ #define NPCM_WTIE BIT(6) /* Enable irq */ @@ -47,6 +85,50 @@ struct npcm_wdt { struct clk *clk; }; +static const struct npcm_wdt_rst_map npcm750_rst_map[] = { + { 0xf000801c, NPCM_WD0RST }, + { 0xf000901c, NPCM_WD1RST }, + { 0xf000a01c, NPCM_WD2RST }, +}; + +static const struct npcm_wdt_status_map npcm750_status_map[] = { + { NPCM_PORST, WDIOF_OVERHEAT }, + { NPCM_CORST, WDIOF_FANFAULT }, + { NPCM_SWR1RST, WDIOF_EXTERN1 }, + { NPCM_SWR2RST, WDIOF_EXTERN2 }, + { NPCM_SWR3RST, WDIOF_POWERUNDER }, + { NPCM_SWR4RST, WDIOF_POWEROVER }, +}; + +static const struct npcm_wdt_data __maybe_unused npcm750_data = { + .rst_map = npcm750_rst_map, + .rst_map_size = ARRAY_SIZE(npcm750_rst_map), + .status_map = npcm750_status_map, + .status_map_size = ARRAY_SIZE(npcm750_status_map), +}; + +static const struct npcm_wdt_rst_map npcm845_rst_map[] = { + { 0xf000801c, NPCM_WD0RST }, + { 0xf000901c, NPCM_WD1RST }, + { 0xf000a01c, NPCM_WD2RST }, +}; + +static const struct npcm_wdt_status_map npcm845_status_map[] = { + { NPCM_PORST, WDIOF_OVERHEAT }, + { NPCM_CORST, WDIOF_FANFAULT }, + { NPCM_SWR1RST, WDIOF_EXTERN1 }, + { NPCM_SWR2RST, WDIOF_EXTERN2 }, + { NPCM_SWR3RST, WDIOF_POWERUNDER }, + { NPCM8XX_TIP_RESET, WDIOF_POWEROVER }, +}; + +static const struct npcm_wdt_data __maybe_unused npcm845_data = { + .rst_map = npcm845_rst_map, + .rst_map_size = ARRAY_SIZE(npcm845_rst_map), + .status_map = npcm845_status_map, + .status_map_size = ARRAY_SIZE(npcm845_status_map), +}; + static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd) { return container_of(wdd, struct npcm_wdt, wdd); @@ -169,6 +251,111 @@ static bool npcm_is_running(struct watchdog_device *wdd) return readl(wdt->reg) & NPCM_WTE; } +static void npcm_get_reset_status(struct npcm_wdt *wdt, struct device *dev, + const struct npcm_wdt_data *data, + resource_size_t start) +{ + struct regmap *gcr_regmap; + u32 rstval = 0; + unsigned int i; + int ret; + + if (!data) + return; + + gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "nuvoton,sysgcr"); + if (IS_ERR(gcr_regmap)) { + dev_warn(dev, + "Failed to find nuvoton,sysgcr, WD reset status not supported\n"); + return; + } + + if (of_device_is_compatible(dev->of_node, "nuvoton,npcm845-wdt")) { + ret = regmap_read(gcr_regmap, NPCM_INTCR2_OFFSET, &rstval); + if (ret) { + dev_warn(dev, "Failed to read INTCR2 reset status: %d\n", + ret); + return; + } + + if (rstval & NPCM_RST) { + ret = regmap_write(gcr_regmap, NPCM_INTCR2_OFFSET, + rstval & ~NPCM_RST); + if (ret) { + dev_warn(dev, + "Failed to clear INTCR2 reset status: %d\n", + ret); + return; + } + + ret = regmap_write(gcr_regmap, NPCM8XX_SCRPAD10_OFFSET, + rstval); + if (ret) { + dev_warn(dev, + "Failed to cache reset status in SCRPAD10: %d\n", + ret); + return; + } + } else { + ret = regmap_read(gcr_regmap, NPCM8XX_SCRPAD10_OFFSET, + &rstval); + if (ret) { + dev_warn(dev, + "Failed to read cached reset status from SCRPAD10: %d\n", + ret); + return; + } + } + } else if (of_device_is_compatible(dev->of_node, "nuvoton,npcm750-wdt")) { + ret = regmap_read(gcr_regmap, NPCM_RESSR_OFFSET, &rstval); + if (ret) { + dev_warn(dev, "Failed to read RESSR reset status: %d\n", + ret); + return; + } + + if (rstval & NPCM_RST) { + ret = regmap_write(gcr_regmap, NPCM_RESSR_OFFSET, + rstval & ~NPCM_RST); + if (ret) { + dev_warn(dev, "Failed to clear RESSR reset status: %d\n", ret); + return; + } + + ret = regmap_write(gcr_regmap, NPCM7XX_SCRPAD2_OFFSET, + rstval); + if (ret) { + dev_warn(dev, + "Failed to cache reset status in SCRPAD2: %d\n", ret); + return; + } + } else { + ret = regmap_read(gcr_regmap, NPCM7XX_SCRPAD2_OFFSET, + &rstval); + if (ret) { + dev_warn(dev, + "Failed to read cached reset status from SCRPAD2: %d\n", + ret); + return; + } + } + } + + for (i = 0; i < data->status_map_size; i++) { + if (rstval & data->status_map[i].rst_bit) + wdt->wdd.bootstatus |= data->status_map[i].wdiof_flag; + } + + for (i = 0; i < data->rst_map_size; i++) { + if (data->rst_map[i].base == start && + rstval & data->rst_map[i].rst_bit) { + wdt->wdd.bootstatus |= WDIOF_CARDRESET; + break; + } + } +} + static const struct watchdog_info npcm_wdt_info = { .identity = KBUILD_MODNAME, .options = WDIOF_SETTIMEOUT @@ -176,6 +363,20 @@ static const struct watchdog_info npcm_wdt_info = { | WDIOF_MAGICCLOSE, }; +static const struct watchdog_info npcm_wdt_rst_info = { + .identity = KBUILD_MODNAME, + .options = WDIOF_SETTIMEOUT + | WDIOF_KEEPALIVEPING + | WDIOF_MAGICCLOSE + | WDIOF_CARDRESET + | WDIOF_OVERHEAT + | WDIOF_FANFAULT + | WDIOF_EXTERN1 + | WDIOF_EXTERN2 + | WDIOF_POWERUNDER + | WDIOF_POWEROVER, +}; + static const struct watchdog_ops npcm_wdt_ops = { .owner = THIS_MODULE, .start = npcm_wdt_start, @@ -188,7 +389,10 @@ static const struct watchdog_ops npcm_wdt_ops = { static int npcm_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + const struct npcm_wdt_data *data = device_get_match_data(dev); + struct resource *res; struct npcm_wdt *wdt; + resource_size_t start; int irq; int ret; @@ -196,10 +400,16 @@ static int npcm_wdt_probe(struct platform_device *pdev) if (!wdt) return -ENOMEM; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + wdt->reg = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(wdt->reg)) return PTR_ERR(wdt->reg); + start = res->start; + wdt->clk = devm_clk_get_optional(&pdev->dev, NULL); if (IS_ERR(wdt->clk)) return PTR_ERR(wdt->clk); @@ -208,7 +418,7 @@ static int npcm_wdt_probe(struct platform_device *pdev) if (irq < 0) return irq; - wdt->wdd.info = &npcm_wdt_info; + wdt->wdd.info = data ? &npcm_wdt_rst_info : &npcm_wdt_info; wdt->wdd.ops = &npcm_wdt_ops; wdt->wdd.min_timeout = 1; wdt->wdd.max_timeout = 2750; @@ -220,6 +430,8 @@ static int npcm_wdt_probe(struct platform_device *pdev) /* Ensure timeout is able to be represented by the hardware */ npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout); + npcm_get_reset_status(wdt, dev, data, start); + if (npcm_is_running(&wdt->wdd)) { /* Restart with the default or device-tree specified timeout */ npcm_wdt_start(&wdt->wdd); @@ -243,7 +455,8 @@ static int npcm_wdt_probe(struct platform_device *pdev) #ifdef CONFIG_OF static const struct of_device_id npcm_wdt_match[] = { {.compatible = "nuvoton,wpcm450-wdt"}, - {.compatible = "nuvoton,npcm750-wdt"}, + {.compatible = "nuvoton,npcm750-wdt", .data = &npcm750_data}, + {.compatible = "nuvoton,npcm845-wdt", .data = &npcm845_data}, {}, }; MODULE_DEVICE_TABLE(of, npcm_wdt_match);