From a17be027dc5ccd51b99b5bc7b487ba9fbdc554e8 Mon Sep 17 00:00:00 2001 From: Sandie Cao Date: Tue, 21 Apr 2026 14:42:00 +0800 Subject: [PATCH 01/35] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05 Document the compatible string for the Deepcomputing fml13v05. It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001. Acked-by: Conor Dooley Signed-off-by: Sandie Cao Reviewed-by: Troy Mitchell Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260421064200.1582367-1-sandie.cao@deepcomputing.io Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index b958b94a924d..af8030242bdc 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -29,6 +29,7 @@ properties: - const: spacemit,k1 - items: - enum: + - deepcomputing,fml13v05 - spacemit,k3-pico-itx - const: spacemit,k3 From 448fedd56cdfa68c2e661b16a8dfc8f3c40a1bcf Mon Sep 17 00:00:00 2001 From: Sandie Cao Date: Tue, 21 Apr 2026 14:43:06 +0800 Subject: [PATCH 02/35] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001. The FML13V05 board features: - SpacemiT K3 RISC-V SoC - LPDDR5 16GB or 32GB - eMMC 32GB ~128GB (Optional) - UFS 3.1 256G (Optional) - QSPI Flash - MicroSD Slot - PCIe-based Wi-Fi - 4 USB-C Ports - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1 - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz) - Port 3 & 4: USB 3.2 Gen 1 This minimal device tree enables booting into a serial console with UART output. Signed-off-by: Sandie Cao Reviewed-by: Troy Mitchell Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260421064306.1583888-1-sandie.cao@deepcomputing.io Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/Makefile | 1 + .../spacemit/k3-deepcomputing-fml13v05.dts | 31 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile index 7e2b87702571..acb993c452ba 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file mode 100644 index 000000000000..b5d5112de358 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 DeepComputing (HK) Limited + */ + +#include "k3.dtsi" +#include "k3-pinctrl.dtsi" + +/ { + model = "DeepComputing FML13V05"; + compatible = "deepcomputing,fml13v05", "spacemit,k3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + memory@100000000 { + device_type = "memory"; + reg = <0x1 0x00000000 0x4 0x00000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; +}; From ece83d42785e12ab7690c0c13b416baf46a74063 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:14 +0800 Subject: [PATCH 03/35] riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2 The adapter is used to access the SpacemiT P1 PMIC present in this board. Tested-by: Vincent Legoll # OrangePi-RV2 Signed-off-by: Han Gao Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/d66f897b179271f508ac5352e52b1223f3bca5fb.1775575436.git.gaohan@iscas.ac.cn Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index 7b7331cb3c72..57ec1cc32b03 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -87,6 +87,12 @@ &pdma { status = "okay"; }; +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; From c02c047b925c0ed101ec6834e1c07a53a45f98d4 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:15 +0800 Subject: [PATCH 04/35] riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2 Define the DC power input and the 4v power as fixed regulator supplies. Define the SpacemiT P1 PMIC voltage regulators and their constraints. Co-developed-by: Chukun Pan Signed-off-by: Chukun Pan Tested-by: Vincent Legoll # OrangePi-RV2 Signed-off-by: Han Gao Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/193370a69e1cc3e4d8c4eb57bfea208e29ac75d8.1775575436.git.gaohan@iscas.ac.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index 57ec1cc32b03..f7a1dadaa95f 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -23,6 +23,25 @@ chosen { stdout-path = "serial0"; }; + vcc_5v0: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc4v0: regulator-vcc4v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc_5v0>; + }; + leds { compatible = "gpio-leds"; @@ -91,6 +110,118 @@ &i2c8 { pinctrl-names = "default"; pinctrl-0 = <&i2c8_cfg>; status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin1-supply = <&vcc4v0>; + vin2-supply = <&vcc4v0>; + vin3-supply = <&vcc4v0>; + vin4-supply = <&vcc4v0>; + vin5-supply = <&vcc4v0>; + vin6-supply = <&vcc4v0>; + aldoin-supply = <&vcc4v0>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4_3v3: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + /* not connected */ + }; + + aldo3 { + /* not connected */ + }; + + aldo4 { + /* not connected */ + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + /* not connected */ + }; + + dldo3 { + /* not connected */ + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + /* not connected */ + }; + }; + }; }; &uart0 { From e3e433dd9aa04448f8f98d59359cab1340d994a3 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:16 +0800 Subject: [PATCH 05/35] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2 Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the OrangePi RV2 board. The board utilizes a Genesys Logic GL3523 USB3.0 hub. Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and PHY-related Device Tree nodes for the OrangePi RV2. Co-developed-by: Chukun Pan Signed-off-by: Chukun Pan Tested-by: Vincent Legoll # OrangePi-RV2 Signed-off-by: Han Gao Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/8e397efb06efd9b02788df07f435ce153de05cd5.1775575436.git.gaohan@iscas.ac.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index f7a1dadaa95f..3a829e3c9cbc 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -23,6 +23,16 @@ chosen { stdout-path = "serial0"; }; + pcie_vcc3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>; + regulator-name = "pcie_vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v0>; + }; + vcc_5v0: regulator-vcc-5v0 { compatible = "regulator-fixed"; regulator-name = "vcc_5v0"; @@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 { vin-supply = <&vcc_5v0>; }; + vcc5v0_usb30: regulator-vcc5v0-usb30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_usb30"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0>; + }; + leds { compatible = "gpio-leds"; @@ -54,6 +74,10 @@ led1 { }; }; +&combo_phy { + status = "okay"; +}; + ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; @@ -224,8 +248,64 @@ dldo7 { }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <&pcie_vcc3v3>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <&pcie_vcc3v3>; +}; + +&pcie2 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + vbus-supply = <&vcc5v0_usb30>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb5e3,610"; + reg = <0x1>; + peer-hub = <&hub_3_0>; + vdd-supply = <&vcc_5v0>; + }; + + hub_3_0: hub@2 { + compatible = "usb5e3,620"; + reg = <0x2>; + peer-hub = <&hub_2_0>; + vdd-supply = <&vcc_5v0>; + }; +}; From 24c12ca43b12c104389d9a159207d0b25779d0af Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 30 Apr 2026 19:52:12 +0100 Subject: [PATCH 06/35] dts: spacemit: set console baud rate on bpif3 Because the default console's baud rate is not set, defconfig kernels do not have any serial output on this platform. Set the baud rate to 115200, matching what is used by U-Boot etc on this platform. Suggested-by: Vivian Wang Fixes: d60d57ab6b2a8 ("riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree") Signed-off-by: Conor Dooley Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260430-reword-overstep-3be08b7eab25@spud Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 5790d927b93d..333ac8ebf3f5 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -19,7 +19,7 @@ aliases { }; chosen { - stdout-path = "serial0"; + stdout-path = "serial0:115200n8"; }; leds { From c580774185426ea316396b1dc3f1737a3ad3800a Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Sat, 2 May 2026 21:30:53 -0400 Subject: [PATCH 07/35] riscv: dts: spacemit: define a SPI controller node Define a node for the fourth SoC SPI controller (number 3) on the SpacemiT K1 SoC. Enable it on the Banana Pi BPI-F3 board, which exposes this feature via its GPIO block: GPIO PIN 19: MOSI GPIO PIN 21: MISO GPIO PIN 23: SCLK GPIO PIN 24: SS (inverted) Define pincontrol configurations for the pins as used on that board. (This was tested using a GigaDevice GD25Q64E SPI NOR chip.) Reviewed-by: Yixun Lan Signed-off-by: Alex Elder Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-3-f412e1ae8a34@riscstar.com Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 7 +++++++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 +++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 15 ++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 333ac8ebf3f5..e20daa50a152 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -14,6 +14,7 @@ aliases { ethernet0 = ð0; ethernet1 = ð1; serial0 = &uart0; + spi3 = &spi3; i2c2 = &i2c2; i2c8 = &i2c8; }; @@ -335,6 +336,12 @@ &pcie2 { status = "okay"; }; +&spi3 { + pinctrl-0 = <&ssp3_0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi index b13dcb10f4d6..34d88334e95e 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -570,4 +570,24 @@ pwm14-1-pins { drive-strength = <32>; }; }; + + ssp3_0_cfg: ssp3-0-cfg { + ssp3-0-pins { + pinmux = , /* SCLK */ + , /* MOSI */ + ; /* MISO */ + + bias-disable; + drive-strength = <19>; + power-source = <3300>; + }; + + ssp3-0-frm-pins { + pinmux = ; /* FRM (frame) */ + + bias-pull-up = <0>; + drive-strength = <19>; + power-source = <3300>; + }; + }; }; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index f0bad6855c97..f8747190d2e1 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -983,6 +983,21 @@ qspi: spi@d420c000 { status = "disabled"; }; + spi3: spi@d401c000 { + compatible = "spacemit,k1-spi"; + reg = <0x0 0xd401c000 0x0 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_SSP3>, + <&syscon_apbc CLK_SSP3_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_SSP3>; + interrupts = <55>; + dmas = <&pdma 20>, <&pdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + /* sec_uart1: 0xf0612000, not available from Linux */ }; From 3c350f6284d8ea5e7a9648241b2e9604f2262d42 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:57:29 +0000 Subject: [PATCH 08/35] dts: riscv: spacemit: correct 32k clock frequency The 32k oscillator's clock frequency is actually 32768Hz, so correct it. Fixes: 67072c8cd48c ("riscv: dts: spacemit: k3: add clock tree") Fixes: a6fafa64b03a ("riscv: dts: spacemit: Add clock tree for SpacemiT K1") Link: https://patch.msgid.link/20260428-06-k3-clk-osc32k-v1-1-e2378da7cb9b@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 2 +- arch/riscv/boot/dts/spacemit/k3.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index f8747190d2e1..24becab4c959 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -333,7 +333,7 @@ vctcxo_3m: clock-3m { osc_32k: clock-32k { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32768>; clock-output-names = "osc_32k"; #clock-cells = <0>; }; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 815debd16409..e6faf8d8759e 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -424,7 +424,7 @@ vctcxo_3m: clock-3m { osc_32k: clock-32k { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32768>; clock-output-names = "osc_32k"; #clock-cells = <0>; }; From f068b204555ad62d6a841a49feb4ea8c4f45b25c Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 9 May 2026 18:00:00 +0800 Subject: [PATCH 09/35] riscv: dts: spacemit: enable eMMC for OrangePi RV2 The OrangePi RV2 board has one eMMC slot, so enable eMMC. Tested using a 16 GiB AJTD4R eMMC module. Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260509100000.3315109-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index 3a829e3c9cbc..c95ca38e3d4a 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -78,6 +78,16 @@ &combo_phy { status = "okay"; }; +&emmc { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; From d3bd58f3060f28ecd30df51925a9b1f62e5e8c9b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 30 Mar 2026 22:15:21 +0000 Subject: [PATCH 10/35] riscv: dts: spacemit: k3: Add USB2.0 support There is one USB2.0 host in K3 SoC which use DWC3 IP but only provide USB2.0 functionality, and with only one USB2 PHY connected. The USB2.0 controller on Pico-ITX board connects to a Terminus FE1.1 Hub which fully USB2.0 protocol compliant and provides 4 ports. Link: https://patch.msgid.link/20260330-02-k3-usb20-dts-v2-1-46af262fb4a9@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 24 +++++++++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 4486dc1fe114..b89c1521e664 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -26,6 +26,14 @@ memory@100000000 { reg = <0x1 0x00000000 0x4 0x00000000>; }; + reg_aux_vcc3v3: regulator-aux-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "AUX_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_aux_vcc5v: regulator-aux-vcc5v { compatible = "regulator-fixed"; regulator-name = "AUX_VCC5V"; @@ -197,3 +205,19 @@ &uart0 { pinctrl-0 = <&uart0_0_cfg>; status = "okay"; }; + +&usb2_host { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub@1 { + compatible = "usb1a40,0101"; + reg = <1>; + vdd-supply = <®_aux_vcc3v3>; + }; +}; + +&usb2_phy { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index e6faf8d8759e..23cca70f796b 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -438,6 +438,37 @@ soc: soc { dma-noncoherent; ranges; + usb2_host: usb@c0a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; + clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; + clock-names = "usbdrd30"; + resets = <&syscon_apmu RESET_APMU_USB2_AHB>, + <&syscon_apmu RESET_APMU_USB2_VCC>, + <&syscon_apmu RESET_APMU_USB2_PHY>; + reset-names = "ahb", "vcc", "phy"; + interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "disabled"; + }; + + usb2_phy: phy@c0a20000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x0 0xc0a20000 0x0 0x200>; + clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; + #phy-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@cac80000 { compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; reg = <0x0 0xcac80000 0x0 0x2000>; From 2d77e577109967ef65f269c1fc1d6a659d4260fb Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:48:59 +0200 Subject: [PATCH 11/35] riscv: dts: spacemit: k1: add SD card controller and pinctrl support Add SD card controller infrastructure for SpacemiT K1 SoC with complete pinctrl support for both standard and UHS modes. - Add sdhci0 controller definition with clocks, resets and interrupts - Add mmc1_cfg pinctrl for 3.3V standard SD operation - Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation - Configure appropriate drive strength and power-source properties This provides complete SD card infrastructure that K1-based boards can enable. Tested-by: Anand Moon Tested-by: Trevor Gamblin Tested-by: Vincent Legoll Reviewed-by: Troy Mitchell Signed-off-by: Iker Pedrosa Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-1-094af27e310d@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++ 2 files changed, 53 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi index 34d88334e95e..4e9a62d0e85b 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -590,4 +590,44 @@ ssp3-0-frm-pins { power-source = <3300>; }; }; + + mmc1_cfg: mmc1-cfg { + mmc1-data-cmd-pins { + pinmux = , /* mmc1_d3 */ + , /* mmc1_d2 */ + , /* mmc1_d1 */ + , /* mmc1_d0 */ + ; /* mmc1_cmd */ + bias-pull-up = <1>; + drive-strength = <19>; + power-source = <3300>; + }; + + mmc1-clk-pins { + pinmux = ; /* mmc1_clk */ + bias-pull-down = <1>; + drive-strength = <19>; + power-source = <3300>; + }; + }; + + mmc1_uhs_cfg: mmc1-uhs-cfg { + mmc1-data-cmd-pins { + pinmux = , /* mmc1_d3 */ + , /* mmc1_d2 */ + , /* mmc1_d1 */ + , /* mmc1_d0 */ + ; /* mmc1_cmd */ + bias-pull-up = <1>; + drive-strength = <42>; + power-source = <1800>; + }; + + mmc1-clk-pins { + pinmux = ; /* mmc1_clk */ + bias-pull-down = <1>; + drive-strength = <42>; + power-source = <1800>; + }; + }; }; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 24becab4c959..06469c364eef 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -1214,6 +1214,19 @@ usb_dwc3: usb@c0a00000 { status = "disabled"; }; + sdhci0: mmc@d4280000 { + compatible = "spacemit,k1-sdhci"; + reg = <0x0 0xd4280000 0x0 0x200>; + clocks = <&syscon_apmu CLK_SDH_AXI>, + <&syscon_apmu CLK_SDH0>; + clock-names = "core", "io"; + resets = <&syscon_apmu RESET_SDH_AXI>, + <&syscon_apmu RESET_SDH0>; + reset-names = "axi", "sdh"; + interrupts = <99>; + status = "disabled"; + }; + emmc: mmc@d4281000 { compatible = "spacemit,k1-sdhci"; reg = <0x0 0xd4281000 0x0 0x200>; From 2585c60ce2f977b13f14a67d1e3ed9c73fd7f381 Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:49:00 +0200 Subject: [PATCH 12/35] riscv: dts: spacemit: k1-orangepi-rv2: add SD card support with UHS modes Add complete SD card controller support with UHS high-speed modes. - Enable sdhci0 controller with 4-bit bus width - Configure card detect GPIO with GPIO_ACTIVE_LOW logic - Connect vmmc-supply to buck4 for 3.3V card power - Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching - Add dual pinctrl states for voltage-dependent pin configuration - Support UHS-I SDR25, SDR50, and SDR104 modes - Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) This enables full SD card functionality including high-speed UHS modes for improved performance. Tested-by: Anand Moon Tested-by: Trevor Gamblin Tested-by: Michael Opdenacker Tested-by: Vincent Legoll Signed-off-by: Iker Pedrosa Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-2-094af27e310d@gmail.com Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-rv2.dts | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index c95ca38e3d4a..bd40bc9011e2 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -17,6 +17,8 @@ aliases { serial0 = &uart0; ethernet0 = ð0; ethernet1 = ð1; + mmc0 = &emmc; + mmc1 = &sdhci0; }; chosen { @@ -202,7 +204,7 @@ buck6 { regulator-always-on; }; - aldo1 { + aldo1: aldo1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -319,3 +321,21 @@ hub_3_0: hub@2 { vdd-supply = <&vcc_5v0>; }; }; + +&sdhci0 { + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&buck4_3v3>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; From c76e2f058cbcab84e4a703f26857a58bdf6a0042 Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:49:01 +0200 Subject: [PATCH 13/35] riscv: dts: spacemit: k1-bananapi-f3: add SD card support with UHS modes Add complete SD card controller support with UHS high-speed modes. - Enable sdhci0 controller with 4-bit bus width - Configure card detect GPIO with GPIO_ACTIVE_LOW and internal pull-up support - Connect vmmc-supply to buck4 for 3.3V card power - Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching - Add dual pinctrl states for voltage-dependent pin configuration - Support UHS-I SDR25, SDR50, and SDR104 modes - Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) This enables full SD card functionality including high-speed UHS modes for improved performance. Suggested-by: Anand Moon Tested-by: Anand Moon Tested-by: Margherita Milani Tested-by: Aurelien Jarno Reviewed-by: Aurelien Jarno Signed-off-by: Iker Pedrosa Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-3-094af27e310d@gmail.com Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 24 +++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index e20daa50a152..72f77e9edd63 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -17,6 +17,8 @@ aliases { spi3 = &spi3; i2c2 = &i2c2; i2c8 = &i2c8; + mmc0 = &emmc; + mmc1 = &sdhci0; }; chosen { @@ -221,7 +223,7 @@ buck3_1v8: buck3 { regulator-always-on; }; - buck4 { + buck4: buck4 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3300000>; regulator-ramp-delay = <5000>; @@ -242,7 +244,7 @@ buck6 { regulator-always-on; }; - aldo1 { + aldo1: aldo1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -374,3 +376,21 @@ hub_3_0: hub@2 { reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; }; }; + +&sdhci0 { + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&buck4>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; From e2dac7c7a3a8970feeeb758f782ce86b89625ebd Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:49 +0200 Subject: [PATCH 14/35] riscv: dts: spacemit: k1-musepi-pro: add PMIC and power infrastructure Enable i2c8 and add the connected SpacemiT P1 PMIC with its related regulators for the board's power infrastructure and voltage regulation support. Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-2-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 29e333b670cf..653e5a1bf41b 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -17,6 +17,7 @@ / { aliases { ethernet0 = ð0; serial0 = &uart0; + i2c8 = &i2c8; }; chosen { @@ -33,6 +34,15 @@ led1 { default-state = "on"; }; }; + + reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "VCC4V0"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-boot-on; + regulator-always-on; + }; }; &emmc { @@ -72,6 +82,130 @@ &pdma { status = "okay"; }; +&i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin1-supply = <®_vcc_4v>; + vin2-supply = <®_vcc_4v>; + vin3-supply = <®_vcc_4v>; + vin4-supply = <®_vcc_4v>; + vin5-supply = <®_vcc_4v>; + vin6-supply = <®_vcc_4v>; + aldoin-supply = <®_vcc_4v>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4_3v3: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + &uart0 { pinctrl-0 = <&uart0_2_cfg>; pinctrl-names = "default"; From 6bc75cfa56e885c2eab80e215f0a610075505846 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:50 +0200 Subject: [PATCH 15/35] riscv: dts: spacemit: k1-musepi-pro: add 24c02 eeprom Enable i2c2 and add the connected GT24C02B EEPROM. It contains an ONIE TLV table: => tlv_eeprom TLV: 0 [ 12.162] TlvInfo Header: [ 12.162] Id String: TlvInfo [ 12.165] Version: 1 [ 12.168] Total Length: 58 [ 12.171] TLV Name Code Len Value [ 12.175] -------------------- ---- --- ----- [ 12.179] Product Name 0x21 16 k1-x_MUSE-Pi-Pro [ 12.184] Serial Number 0x23 17 BPMIMXXXXXXXXXXXX [ 12.189] Unknown 0x41 1 0x02 [ 12.194] Base MAC Address 0x24 6 FE:FE:FE:XX:XX:XX [ 12.199] MAC Addresses 0x2A 2 2 [ 12.203] CRC-32 0xFE 4 0x395ECD34 [ 12.207] Checksum is valid. (With 0x41 as TLV_CODE_DDR_CSNUM) Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-3-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 653e5a1bf41b..b8e73eed8e62 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -17,6 +17,7 @@ / { aliases { ethernet0 = ð0; serial0 = &uart0; + i2c2 = &i2c2; i2c8 = &i2c8; }; @@ -82,6 +83,38 @@ &pdma { status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_0_cfg>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ + pagesize = <8>; + read-only; + size = <256>; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + product-name { + }; + + serial-number { + }; + + mac-address { + #nvmem-cell-cells = <1>; + }; + + num-macs { + }; + }; + }; +}; + &i2c8 { pinctrl-0 = <&i2c8_cfg>; pinctrl-names = "default"; From 735b1b205d07bf7bfa55b1f50f5485b9cc42a251 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:51 +0200 Subject: [PATCH 16/35] riscv: dts: spacemit: k1-musepi-pro: enable QSPI and add SPI NOR Add the QSPI controller node and describe the attached SPI NOR flash (Winbond W25Q64FWSSAQ). Add a corresponding vendor flash partition layout. Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-4-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index b8e73eed8e62..74841cffd5f5 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -44,6 +44,15 @@ reg_vcc_4v: regulator-vcc-4v { regulator-boot-on; regulator-always-on; }; + + reg_qspi_vcc1v833: regulator-qspi-vcc1v833 { + compatible = "regulator-fixed"; + regulator-name = "QSPI_VCC1833"; + regulator-min-microvolt = <1833000>; + regulator-max-microvolt = <1833000>; + regulator-always-on; + vin-supply = <&buck4_3v3>; + }; }; &emmc { @@ -239,6 +248,47 @@ dldo7 { }; }; +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <®_qspi_vcc1v833>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x0 0x10000>; + }; + private@10000 { + reg = <0x10000 0x10000>; + }; + fsbl@20000 { + reg = <0x20000 0x40000>; + }; + env@60000 { + reg = <0x60000 0x10000>; + }; + opensbi@70000 { + reg = <0x70000 0x30000>; + }; + uboot@a0000 { + reg = <0xa0000 0x760000>; + }; + }; + }; +}; + &uart0 { pinctrl-0 = <&uart0_2_cfg>; pinctrl-names = "default"; From 83c658c7a82304a2bc944cdd4a5b4f98d19322f0 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:52 +0200 Subject: [PATCH 17/35] riscv: dts: spacemit: k1-musepi-pro: enable USB 3 ports Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) and usbphy2 (USB 2 PHY) on the MusePi Pro board. The board uses a VLI VL817 hub, providing four ports. Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-5-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 74841cffd5f5..b284bf416880 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -53,6 +53,26 @@ reg_qspi_vcc1v833: regulator-qspi-vcc1v833 { regulator-always-on; vin-supply = <&buck4_3v3>; }; + + reg_5v_vbus: regulator-5v-vbus { + compatible = "regulator-fixed"; + regulator-name = "5V_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio K1_GPIO(79) GPIO_ACTIVE_HIGH>; /* USB3_PWREN */ + enable-active-high; + }; + + reg_vcc5v_hub: regulator-vcc5v-hub { + compatible = "regulator-fixed"; + regulator-name = "VCC5V0_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; /* HUB_PWREN */ + enable-active-high; + }; }; &emmc { @@ -65,6 +85,10 @@ &emmc { status = "okay"; }; +&combo_phy { + status = "okay"; +}; + ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; @@ -294,3 +318,31 @@ &uart0 { pinctrl-names = "default"; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + vbus-supply = <®_5v_vbus>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; + vdd-supply = <®_vcc5v_hub>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ + }; + + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; + vdd-supply = <®_vcc5v_hub>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ + }; +}; From d9ab0a855ba13f1db3ae16539348714c74010a22 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:53 +0200 Subject: [PATCH 18/35] riscv: dts: spacemit: k1-musepi-pro: enable PCIe ports Enable the two PCIe controllers along with their associated PHYs. They are routed to the M.2 M-key connector and to the PCIe slot. Signed-off-by: Andre Heider Link: https://patch.msgid.link/20260513071958.29574-6-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index b284bf416880..898b537ba0bc 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -36,6 +36,14 @@ led1 { }; }; + reg_pcie_vcc_3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_vcc_4v: regulator-vcc-4v { compatible = "regulator-fixed"; regulator-name = "VCC4V0"; @@ -272,6 +280,36 @@ dldo7 { }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <®_pcie_vcc_3v3>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <®_pcie_vcc_3v3>; +}; + +&pcie2 { + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&qspi_cfg>; From f125c6085fd775f09a316f61cc89a0ae86826895 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Wed, 13 May 2026 09:19:54 +0200 Subject: [PATCH 19/35] riscv: dts: spacemit: k1-musepi-pro: set default console baud rate Allow serial output with the same uboot/opensbi settings so the console works without providing a cmdline. Signed-off-by: Andre Heider Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260513071958.29574-7-a.heider@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 898b537ba0bc..4aef287353ca 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -22,7 +22,7 @@ aliases { }; chosen { - stdout-path = "serial0"; + stdout-path = "serial0:115200n8"; }; leds { From e2518e8cb1dde64af2d1bb246639bb7ef7523f7a Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 16 May 2026 16:00:30 +0800 Subject: [PATCH 20/35] riscv: dts: spacemit: enable QSPI for OrangePi RV2 Enable the QSPI controller and the XM25QU128C SPI NOR flash on the OrangePi RV2 board. Add a flash partition layout from vendor UBoot. Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260516080030.1736836-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-rv2.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index bd40bc9011e2..7c49bce427f3 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -290,6 +290,51 @@ &pcie2 { status = "okay"; }; +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <&buck3_1v8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x00000 0x010000>; + }; + + private@10000 { + reg = <0x10000 0x010000>; + }; + + fsbl@20000 { + reg = <0x20000 0x040000>; + }; + + env@60000 { + reg = <0x60000 0x010000>; + }; + + opensbi@70000 { + reg = <0x70000 0x030000>; + }; + + uboot@a0000 { + reg = <0xa0000 0x760000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; From 3f47ca8bb3c3f4a71688451a0cb7350d3e1e1059 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Mon, 18 May 2026 11:32:44 +0800 Subject: [PATCH 21/35] riscv: dts: spacemit: Add PDMA controller node for K3 SoC Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. The PDMA controller provides general-purpose DMA capabilities for various peripheral devices across the system to offload CPU data transfers. Unlike the previous K1 SoC, where some DMA masters had memory addressing limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus with dma-ranges to restrict memory allocations, the K3 DMA masters have full memory addressing capabilities. Therefore, the PDMA node is now instantiated directly under the main soc bus. Signed-off-by: Troy Mitchell Link: https://patch.msgid.link/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 23cca70f796b..d4be8de8fc6c 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -586,6 +586,17 @@ gmac2_axi_setup: stmmac-axi-config { }; }; + pdma: dma-controller@d4000000 { + compatible = "spacemit,k3-pdma"; + reg = <0x0 0xd4000000 0x0 0x4000>; + clocks = <&syscon_apmu CLK_APMU_DMA>; + resets = <&syscon_apmu RESET_APMU_DMA>; + interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <16>; + #dma-cells = <1>; + status = "disabled"; + }; + i2c0: i2c@d4010800 { compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; reg = <0x0 0xd4010800 0x0 0x38>; From 247c77ff5806bcd6a5ff802718de1f0aa2bcba6c Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Mon, 27 Apr 2026 15:15:17 +0800 Subject: [PATCH 22/35] riscv: dts: spacemit: Add thermal sensor for K1 SoC Include the Thermal Sensor node in the SpacemiT K1 dtsi with definitions for registers, clocks, and interrupts. Additionally, configure thermal zones for the soc, package, gpu, and clusters to enable temperature monitoring via the thermal framework. Tested-by: Vincent Legoll # OrangePi-RV2 Tested-by: Gong Shuai Signed-off-by: Shuwei Wu Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260427-k1-thermal-v5-3-df39187480ed@mailbox.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 101 +++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 06469c364eef..08a0f28d011f 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -339,6 +339,96 @@ osc_32k: clock-32k { }; }; + thermal-zones { + soc-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 0>; + + trips { + soc-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 1>; + + trips { + package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&thermal 2>; + + trips { + gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&thermal 3>; + + trips { + cluster0-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&thermal 4>; + + trips { + cluster1-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster1-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -494,6 +584,17 @@ syscon_apbc: system-controller@d4015000 { #reset-cells = <1>; }; + thermal: thermal@d4018000 { + compatible = "spacemit,k1-tsensor"; + reg = <0x0 0xd4018000 0x0 0x100>; + clocks = <&syscon_apbc CLK_TSEN>, + <&syscon_apbc CLK_TSEN_BUS>; + clock-names = "core", "bus"; + interrupts = <61>; + resets = <&syscon_apbc RESET_TSEN>; + #thermal-sensor-cells = <1>; + }; + i2c6: i2c@d4018800 { compatible = "spacemit,k1-i2c"; reg = <0x0 0xd4018800 0x0 0x38>; From c5ad6737df88bd3c3e83145edb25737cb19f9a1f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 May 2026 18:00:30 +0800 Subject: [PATCH 23/35] riscv: dts: spacemit: enable USB3 on OrangePi R2S Enable the DWC3 USB3.0 controller and its associated PHY on the OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 ports, but the USB2 ports are handled by a separate controller. Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260518100030.2354606-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-r2s.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts index de75f6aac740..1ecc40749e5a 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -21,6 +21,19 @@ aliases { chosen { stdout-path = "serial0"; }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio K1_GPIO(126) GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combo_phy { + status = "okay"; }; &emmc { @@ -90,3 +103,13 @@ &uart0 { pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + vbus-supply = <&vcc5v0_usb>; + status = "okay"; +}; From 4f97acb4f744f516bbe976da8282c0fe213216ff Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:35 +0200 Subject: [PATCH 24/35] riscv: dts: spacemit: set console baud rate on Milk-V Jupiter Because the default console's baud rate is not set, defconfig kernels do not have any serial output on this platform. Set the baud rate to 115200, matching what is used by U-Boot etc on this platform. See-also: 24c12ca43b12c ("dts: spacemit: set console baud rate on bpif3") Fixes: 5b90a3d6092d9 ("riscv: dts: spacemit: Add Milk-V Jupiter board device tree") Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-2-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index afaad59e6bce..db98dbfadf00 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -20,7 +20,7 @@ aliases { }; chosen { - stdout-path = "serial0"; + stdout-path = "serial0:115200n8"; }; leds { From 9cdeba29d65b10e7bdb1491167141ff2df238ab8 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:36 +0200 Subject: [PATCH 25/35] riscv: dts: spacemit: sort aliases on Milk-V Jupiter Before adding more aliases, just sort them. Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-3-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index db98dbfadf00..fbba33992347 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -14,9 +14,9 @@ / { aliases { ethernet0 = ð0; ethernet1 = ð1; - serial0 = &uart0; i2c2 = &i2c2; i2c8 = &i2c8; + serial0 = &uart0; }; chosen { From 4bc9f44d581be66718cf7cf6e649fb92b3c2e6c6 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:37 +0200 Subject: [PATCH 26/35] riscv: dts: spacemit: enable eMMC on Milk-V Jupiter The Milk-V Jupiter board has a connector for an eMMC module. Add an entry for it in the device tree and alias it mmc0. Mark the device as non-removable as eMMC modules have no CD pin and are not supposed to be inserted or removed while the system is running. On systems without an eMMC module installed, the kernel emits the following informational message during boot: mmc0: SDHCI controller on d4281000.mmc [d4281000.mmc] using ADMA mmc0: Failed to initialize a non-removable card Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-4-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index fbba33992347..1a833e716cb6 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -16,6 +16,7 @@ aliases { ethernet1 = ð1; i2c2 = &i2c2; i2c8 = &i2c8; + mmc0 = &emmc; serial0 = &uart0; }; @@ -105,6 +106,16 @@ &combo_phy { status = "okay"; }; +&emmc { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; From 60b5e027c8c8cab69ad9cc7cab71ee795963e7b1 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:38 +0200 Subject: [PATCH 27/35] riscv: dts: spacemit: enable SD card support on Milk-V Jupiter Add complete SD card controller support with UHS high-speed modes. - Enable sdhci0 controller with 4-bit bus width - Configure card detect GPIO with pull-up - Connect vmmc-supply to buck4 for 3.3V card power - Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching - Add dual pinctrl states for voltage-dependent pin configuration - Support UHS-I SDR25, SDR50, and SDR104 modes - Alias it as mmc1 Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-5-aurelien@aurel32.net Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-milkv-jupiter.dts | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 1a833e716cb6..beebf804197e 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -17,6 +17,7 @@ aliases { i2c2 = &i2c2; i2c8 = &i2c8; mmc0 = &emmc; + mmc1 = &sdhci0; serial0 = &uart0; }; @@ -250,7 +251,7 @@ buck6 { regulator-always-on; }; - aldo1 { + aldo1: aldo1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -385,6 +386,24 @@ uboot@a00000 { }; }; +&sdhci0 { + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&buck4_3v3>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; From 6edd9a0d32e1ef81133b8cb5b3bb3157a44da4d1 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:39 +0200 Subject: [PATCH 28/35] riscv: dts: spacemit: fix uboot partition offset on Milk-V Jupiter Correct the uboot partition node name to match its actual offset. Fixes: 2829823956f0 ("riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter") Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260519041458.3287843-6-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index beebf804197e..2fc8d6533786 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -379,7 +379,7 @@ env@60000 { opensbi@70000 { reg = <0x70000 0x30000>; }; - uboot@a00000 { + uboot@a0000 { reg = <0xa0000 0x760000>; }; }; From 844c29197366e25ad361cf725d80acb4f10e3e19 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 21 May 2026 00:24:41 +0000 Subject: [PATCH 29/35] riscv: dts: spacemit: k3: Add pwm support Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents the pinctrl info which would easily help to enable them in future. Link: https://patch.msgid.link/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 590 +++++++++++++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 220 +++++++ 2 files changed, 810 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 23899d3f308a..252c64af76fe 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -56,6 +56,596 @@ i2c8-pins { }; }; + /omit-if-no-ref/ + pwm0_0_cfg: pwm0-0-cfg { + pwm0-0-pins { + pinmux = ; /* pwm0 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm0_1_cfg: pwm0-1-cfg { + pwm0-1-pins { + pinmux = ; /* pwm0 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm1_0_cfg: pwm1-0-cfg { + pwm1-0-pins { + pinmux = ; /* pwm1 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm1_1_cfg: pwm1-1-cfg { + pwm1-1-pins { + pinmux = ; /* pwm1 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm1_2_cfg: pwm1-2-cfg { + pwm1-2-pins { + pinmux = ; /* pwm1 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm2_0_cfg: pwm2-0-cfg { + pwm2-0-pins { + pinmux = ; /* pwm2 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm2_1_cfg: pwm2-1-cfg { + pwm2-1-pins { + pinmux = ; /* pwm2 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm2_2_cfg: pwm2-2-cfg { + pwm2-2-pins { + pinmux = ; /* pwm2 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm2_3_cfg: pwm2-3-cfg { + pwm2-3-pins { + pinmux = ; /* pwm2 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm3_0_cfg: pwm3-0-cfg { + pwm3-0-pins { + pinmux = ; /* pwm3 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm3_1_cfg: pwm3-1-cfg { + pwm3-1-pins { + pinmux = ; /* pwm3 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm3_2_cfg: pwm3-2-cfg { + pwm3-2-pins { + pinmux = ; /* pwm3 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm3_3_cfg: pwm3-3-cfg { + pwm3-3-pins { + pinmux = ; /* pwm3 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm4_0_cfg: pwm4-0-cfg { + pwm4-0-pins { + pinmux = ; /* pwm4 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm4_1_cfg: pwm4-1-cfg { + pwm4-1-pins { + pinmux = ; /* pwm4 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm4_2_cfg: pwm4-2-cfg { + pwm4-2-pins { + pinmux = ; /* pwm4 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm5_0_cfg: pwm5-0-cfg { + pwm5-0-pins { + pinmux = ; /* pwm5 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm5_1_cfg: pwm5-1-cfg { + pwm5-1-pins { + pinmux = ; /* pwm5 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm5_2_cfg: pwm5-2-cfg { + pwm5-2-pins { + pinmux = ; /* pwm5 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm6_0_cfg: pwm6-0-cfg { + pwm6-0-pins { + pinmux = ; /* pwm6 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm6_1_cfg: pwm6-1-cfg { + pwm6-1-pins { + pinmux = ; /* pwm6 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm6_2_cfg: pwm6-2-cfg { + pwm6-2-pins { + pinmux = ; /* pwm6 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm7_0_cfg: pwm7-0-cfg { + pwm7-0-pins { + pinmux = ; /* pwm7 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm7_1_cfg: pwm7-1-cfg { + pwm7-1-pins { + pinmux = ; /* pwm7 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm7_2_cfg: pwm7-2-cfg { + pwm7-2-pins { + pinmux = ; /* pwm7 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm8_0_cfg: pwm8-0-cfg { + pwm8-0-pins { + pinmux = ; /* pwm8 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm8_1_cfg: pwm8-1-cfg { + pwm8-1-pins { + pinmux = ; /* pwm8 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm8_2_cfg: pwm8-2-cfg { + pwm8-2-pins { + pinmux = ; /* pwm8 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm9_0_cfg: pwm9-0-cfg { + pwm9-0-pins { + pinmux = ; /* pwm9 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm9_1_cfg: pwm9-1-cfg { + pwm9-1-pins { + pinmux = ; /* pwm9 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm9_2_cfg: pwm9-2-cfg { + pwm9-2-pins { + pinmux = ; /* pwm9 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm10_0_cfg: pwm10-0-cfg { + pwm10-0-pins { + pinmux = ; /* pwm10 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm10_1_cfg: pwm10-1-cfg { + pwm10-1-pins { + pinmux = ; /* pwm10 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm10_2_cfg: pwm10-2-cfg { + pwm10-2-pins { + pinmux = ; /* pwm10 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm11_0_cfg: pwm11-0-cfg { + pwm11-0-pins { + pinmux = ; /* pwm11 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm11_1_cfg: pwm11-1-cfg { + pwm11-1-pins { + pinmux = ; /* pwm11 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm12_0_cfg: pwm12-0-cfg { + pwm12-0-pins { + pinmux = ; /* pwm12 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm12_1_cfg: pwm12-1-cfg { + pwm12-1-pins { + pinmux = ; /* pwm12 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm13_0_cfg: pwm13-0-cfg { + pwm13-0-pins { + pinmux = ; /* pwm13 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm13_1_cfg: pwm13-1-cfg { + pwm13-1-pins { + pinmux = ; /* pwm13 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm13_2_cfg: pwm13-2-cfg { + pwm13-2-pins { + pinmux = ; /* pwm13 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm14_0_cfg: pwm14-0-cfg { + pwm14-0-pins { + pinmux = ; /* pwm14 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm14_1_cfg: pwm14-1-cfg { + pwm14-1-pins { + pinmux = ; /* pwm14 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm14_2_cfg: pwm14-2-cfg { + pwm14-2-pins { + pinmux = ; /* pwm14 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm15_0_cfg: pwm15-0-cfg { + pwm15-0-pins { + pinmux = ; /* pwm15 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm15_1_cfg: pwm15-1-cfg { + pwm15-1-pins { + pinmux = ; /* pwm15 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm15_2_cfg: pwm15-2-cfg { + pwm15-2-pins { + pinmux = ; /* pwm15 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm16_0_cfg: pwm16-0-cfg { + pwm16-0-pins { + pinmux = ; /* pwm16 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm16_1_cfg: pwm16-1-cfg { + pwm16-1-pins { + pinmux = ; /* pwm16 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm16_2_cfg: pwm16-2-cfg { + pwm16-2-pins { + pinmux = ; /* pwm16 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm17_0_cfg: pwm17-0-cfg { + pwm17-0-pins { + pinmux = ; /* pwm17 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm17_1_cfg: pwm17-1-cfg { + pwm17-1-pins { + pinmux = ; /* pwm17 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm17_2_cfg: pwm17-2-cfg { + pwm17-2-pins { + pinmux = ; /* pwm17 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm18_0_cfg: pwm18-0-cfg { + pwm18-0-pins { + pinmux = ; /* pwm18 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm18_1_cfg: pwm18-1-cfg { + pwm18-1-pins { + pinmux = ; /* pwm18 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm18_2_cfg: pwm18-2-cfg { + pwm18-2-pins { + pinmux = ; /* pwm18 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm19_0_cfg: pwm19-0-cfg { + pwm19-0-pins { + pinmux = ; /* pwm19 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm19_1_cfg: pwm19-1-cfg { + pwm19-1-pins { + pinmux = ; /* pwm19 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + pwm19_2_cfg: pwm19-2-cfg { + pwm19-2-pins { + pinmux = ; /* pwm19 */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + /omit-if-no-ref/ uart0_0_cfg: uart0-0-cfg { uart0-0-pins { diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index d4be8de8fc6c..fa459bc95688 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -839,6 +839,226 @@ i2c8: i2c@d401d800 { status = "disabled"; }; + pwm0: pwm@d401a000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401a000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM0>, + <&syscon_apbc CLK_APBC_PWM0_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM0>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@d401a400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401a400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM1>, + <&syscon_apbc CLK_APBC_PWM1_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM1>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@d401a800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401a800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM2>, + <&syscon_apbc CLK_APBC_PWM2_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM2>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@d401ac00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401ac00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM3>, + <&syscon_apbc CLK_APBC_PWM3_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM3>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@d401b000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401b000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM4>, + <&syscon_apbc CLK_APBC_PWM4_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@d401b400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401b400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM5>, + <&syscon_apbc CLK_APBC_PWM5_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@d401b800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401b800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM6>, + <&syscon_apbc CLK_APBC_PWM6_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@d401bc00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401bc00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM7>, + <&syscon_apbc CLK_APBC_PWM7_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM7>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@d4020000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM8>, + <&syscon_apbc CLK_APBC_PWM8_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM8>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@d4020400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM9>, + <&syscon_apbc CLK_APBC_PWM9_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM9>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@d4020800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM10>, + <&syscon_apbc CLK_APBC_PWM10_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@d4020c00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020c00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM11>, + <&syscon_apbc CLK_APBC_PWM11_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM11>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@d4021000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM12>, + <&syscon_apbc CLK_APBC_PWM12_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM12>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@d4021400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM13>, + <&syscon_apbc CLK_APBC_PWM13_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM13>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@d4021800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM14>, + <&syscon_apbc CLK_APBC_PWM14_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM14>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@d4021c00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021c00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM15>, + <&syscon_apbc CLK_APBC_PWM15_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM15>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm16: pwm@d4022000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM16>, + <&syscon_apbc CLK_APBC_PWM16_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM16>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm17: pwm@d4022400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM17>, + <&syscon_apbc CLK_APBC_PWM17_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM17>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm18: pwm@d4022800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM18>, + <&syscon_apbc CLK_APBC_PWM18_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM18>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm19: pwm@d4022c00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022c00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM19>, + <&syscon_apbc CLK_APBC_PWM19_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM19>; + #pwm-cells = <3>; + status = "disabled"; + }; + pinctrl: pinctrl@d401e000 { compatible = "spacemit,k3-pinctrl"; reg = <0x0 0xd401e000 0x0 0x1000>; From 85e4c5733cd7efa39f10d7200095c016ce4a2815 Mon Sep 17 00:00:00 2001 From: Trevor Gamblin Date: Wed, 20 May 2026 15:06:23 +0200 Subject: [PATCH 30/35] riscv: dts: spacemit: k1-musepi-pro: add SD card support with UHS modes Update the Muse Pi Pro devicetree with SD card support to match what was done for the OrangePi RV2 in [1]. More precisely: - Enable sdhci0 controller with 4-bit bus width - Configure card detect GPIO with internal pull-up support - Connect vmmc-supply to buck4 for 3.3V card power - Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching - Add dual pinctrl states for voltage-dependent pin configuration - Support UHS-I SDR25, SDR50, and SDR104 modes - Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) [1] https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# Tested-by: Andre Heider Signed-off-by: Trevor Gamblin Signed-off-by: Iker Pedrosa Signed-off-by: Andre Heider Link: https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# Link: https://patch.msgid.link/20260520130624.1763487-1-a.heider@gmail.com Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 4aef287353ca..0d809e4ad3b1 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -19,6 +19,8 @@ aliases { serial0 = &uart0; i2c2 = &i2c2; i2c8 = &i2c8; + mmc0 = &emmc; + mmc1 = &sdhci0; }; chosen { @@ -218,7 +220,7 @@ buck6 { regulator-always-on; }; - aldo1 { + aldo1: aldo1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -384,3 +386,21 @@ hub_3_0: hub@2 { reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ }; }; + +&sdhci0 { + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&buck4_3v3>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; From 3abf3f5c84fd32a95132a403e0209c8010b227f8 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 20 May 2026 23:45:27 +0000 Subject: [PATCH 31/35] dt-bindings: riscv: spacemit: Add K3 CoM260-IFX board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module with a reference carrier board. The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD card slot and includes interfaces such as dual MIPI CSI-2 connectors, M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin expansion header. The carrier board is intended as a general-purpose development platform for CoM260 module and exposes interfaces for all of storage, display, networking, and camera connectivity. Acked-by: Conor Dooley Link: https://patch.msgid.link/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index af8030242bdc..311bbccba0ba 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -32,6 +32,11 @@ properties: - deepcomputing,fml13v05 - spacemit,k3-pico-itx - const: spacemit,k3 + - items: + - enum: + - spacemit,k3-com260-ifx + - const: spacemit,k3-com260 + - const: spacemit,k3 additionalProperties: true From cfe5c91cb73c87f9021e446ec9d323c483851c46 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 20 May 2026 23:45:28 +0000 Subject: [PATCH 32/35] riscv: dts: spacemit: k3: Initial support for CoM260-IFX board The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer module with a carrier board. The module integrates the K3 SoC, LPDDR5, UFS storage, Gigabit Ethernet, Micro SD card, PMIC Chip. The board offers a comprehensive array of interfaces, including MIPI-DSI, MIPI-CSI, DisplayPort, SDIO, SPI, I2S, I2C, CAN-FD, PWM, UART, USB, PCIe, and GMAC. Add initial support for enabling Serial UART and ethernet. Link: https://patch.msgid.link/20260520-02-k3-com260-ifx-v2-2-d55095457cf0@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/Makefile | 1 + .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 21 ++ arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 190 ++++++++++++++++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 +++ 4 files changed, 245 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260.dtsi diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile index acb993c452ba..28ec9e1e0a62 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-com260-ifx.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts new file mode 100644 index 000000000000..238bb03d0e9e --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Yixun Lan + */ + +#include "k3-com260.dtsi" + +/ { + model = "SpacemiT K3 CoM260 IFX"; + compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3"; + + aliases { + serial0 = &uart0; + ethernet0 = ð1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi new file mode 100644 index 000000000000..a38d7b738258 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Yixun Lan + */ +#include + +#include "k3.dtsi" +#include "k3-pinctrl.dtsi" + +/ { + model = "SpacemiT K3 CoM260 Module"; + compatible = "spacemit,k3-com260", "spacemit,k3"; + + memory@100000000 { + device_type = "memory"; + reg = <0x1 0x00000000 0x4 0x00000000>; + }; + + reg_5v_sys: regulator-5v-sys { + compatible = "regulator-fixed"; + regulator-name = "P5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + vin1-supply = <®_5v_sys>; + vin2-supply = <®_5v_sys>; + vin3-supply = <®_5v_sys>; + vin4-supply = <®_5v_sys>; + vin5-supply = <®_5v_sys>; + vin6-supply = <®_5v_sys>; + aldoin-supply = <®_5v_sys>; + dldoin1-supply = <&buck4>; + dldoin2-supply = <&buck4>; + + regulators { + buck1: buck1 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2: buck2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3: buck3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4: buck4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6: buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1: aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo3: aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4: aldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo1: dldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo2: dldo2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo3: dldo3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo4: dldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + dldo5: dldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo6: dldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo7: dldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +ð1 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rgmii_0_cfg>, <&gmac1_phy_0_cfg>; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + status = "okay"; + + mdio { + phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 252c64af76fe..3ee1471f3798 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -45,6 +45,39 @@ gmac0-phy-0-pins { }; }; + gmac1_rgmii_0_cfg: gmac1-rgmii-0-cfg { + gmac1-rgmii-0-pins { + pinmux = , /* gmac1_rxdv */ + , /* gmac1 rx d0 */ + , /* gmac1 rx d1 */ + , /* gmac1 rx_clk */ + , /* gmac1 rx d2 */ + , /* gmac1 rx d3 */ + , /* gmac1 tx d0 */ + , /* gmac1 tx d1 */ + , /* gmac1 tx clk */ + , /* gmac1 tx d2 */ + , /* gmac1 tx d3 */ + , /* gmac1 tx_en */ + , /* gmac1 mdc */ + ; /* gmac1 mdio */ + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + }; + + gmac1_phy_0_cfg: gmac1-phy-0-cfg { + gmac1-phy-0-pins { + pinmux = ; /* gmac1 int */ + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + }; + /omit-if-no-ref/ i2c8_cfg: i2c8-cfg { i2c8-pins { From b4a789799d4c2be03a2c9a4e06f3ea817bb04416 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 26 May 2026 15:22:58 -0400 Subject: [PATCH 33/35] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse provides a forward progress guarantee on LR/SC sequences in main memory regions with cacheability and coherence PMAs. The SpacemiT X100 core supports it per the SpacemiT K3 hardware specification. Signed-off-by: Guodong Xu Reviewed-by: Yixun lan Link: https://patch.msgid.link/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index fa459bc95688..223e66721bf9 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -36,7 +36,7 @@ cpu_0: cpu@0 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -77,7 +77,7 @@ cpu_1: cpu@1 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -118,7 +118,7 @@ cpu_2: cpu@2 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -159,7 +159,7 @@ cpu_3: cpu@3 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -200,7 +200,7 @@ cpu_4: cpu@4 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -241,7 +241,7 @@ cpu_5: cpu@5 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -282,7 +282,7 @@ cpu_6: cpu@6 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", @@ -323,7 +323,7 @@ cpu_7: cpu@7 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", - "ziccamoa", "ziccif", "zicclsm", "zicntr", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", From 3ea695eb111fc5a7ffddd21d5c3fee6d82560413 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 18 May 2026 20:58:16 +0000 Subject: [PATCH 34/35] dts: riscv: spacemit: k3: Fix I/O power settings SpacemiT K3 SoC support dual-voltage I/O power domain, while initially configure to 3.3v, and need to access register from APBC space to switch to 1.8v domain. Fix the GMAC0's I/O pins 1.8v switch failure that will result a broken ethernet driver. Fixes: d8944577496b ("riscv: dts: spacemit: k3: add pinctrl support") Reported-by: Han Gao Link: https://patch.msgid.link/20260518-07-dts-pinctrl-io-power-v1-1-abe19c14a726@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 223e66721bf9..19fc9b49668e 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -1065,6 +1065,7 @@ pinctrl: pinctrl@d401e000 { clocks = <&syscon_apbc CLK_APBC_AIB>, <&syscon_apbc CLK_APBC_AIB_BUS>; clock-names = "func", "bus"; + spacemit,apbc = <&syscon_apbc>; }; uart10: serial@d401f000 { From 793cc54475b49b5b558902b5c13e4bfe66530a50 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 20 May 2026 18:00:00 +0800 Subject: [PATCH 35/35] riscv: dts: spacemit: enable PMIC on OrangePi R2S Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and its associated regulators to support voltage regulation on the board. Signed-off-by: Chukun Pan Reviewed-by: Yixun lan Link: https://patch.msgid.link/20260520100000.575719-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-r2s.dts | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts index 1ecc40749e5a..b13a8d6a2670 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -13,6 +13,7 @@ / { compatible = "xunlong,orangepi-r2s", "spacemit,k1"; aliases { + i2c8 = &i2c8; serial0 = &uart0; ethernet0 = ð0; ethernet1 = ð1; @@ -22,6 +23,15 @@ chosen { stdout-path = "serial0"; }; + vcc4v0: regulator-vcc4v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + }; + vcc5v0_usb: regulator-vcc5v0-usb { compatible = "regulator-fixed"; enable-active-high; @@ -94,6 +104,130 @@ rgmii1: phy@1 { }; }; +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin1-supply = <&vcc4v0>; + vin2-supply = <&vcc4v0>; + vin3-supply = <&vcc4v0>; + vin4-supply = <&vcc4v0>; + vin5-supply = <&vcc4v0>; + vin6-supply = <&vcc4v0>; + aldoin-supply = <&vcc4v0>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4_3v3: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1_3v3: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + &pdma { status = "okay"; };