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drm/amdgpu: add ih ip block for dimgrey_cavefish

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Enable ih block for dimgrey_cavefish, same as navy_flounder.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tao Zhou 2020-10-02 11:39:28 -04:00 committed by Alex Deucher
parent 3e02ad4476
commit 771cc67ed0
2 changed files with 2 additions and 0 deletions
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1
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
View File

@ -315,6 +315,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH:
ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);

1
drivers/gpu/drm/amd/amdgpu/nv.c
View File

@ -629,6 +629,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_DIMGREY_CAVEFISH:
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
break;
default:
return -EINVAL;