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arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Fix the PCIe iommu-map entries

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The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe
iommu-map entries specify only one cell for the SID, omitting the SID
mask. This went unnoticed until the OF core started warning with commit
ccb2fd725d ("of: Respect #{iommu,msi}-cells in maps"):

  iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output

So fix the entries to match the provider's '#iommu-cells' property.

Fixes: 4559b435f7 ("arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-22-83405d37ba41@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Manivannan Sadhasivam 2026-07-30 13:56:03 +02:00 committed by Bjorn Andersson
parent 485dc5e557
commit 770d144843
1 changed files with 25 additions and 25 deletions
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50
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
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@ -54,15 +54,15 @@ &pcie0 {
pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
pinctrl-names = "default";
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>,
<0x208 &apps_smmu 0x1c04 0x1>,
<0x210 &apps_smmu 0x1c05 0x1>,
<0x218 &apps_smmu 0x1c06 0x1>,
<0x300 &apps_smmu 0x1c07 0x1>,
<0x400 &apps_smmu 0x1c08 0x1>,
<0x500 &apps_smmu 0x1c09 0x1>,
<0x501 &apps_smmu 0x1c10 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>,
<0x100 &apps_smmu 0x1c01 0x0 0x1>,
<0x208 &apps_smmu 0x1c04 0x0 0x1>,
<0x210 &apps_smmu 0x1c05 0x0 0x1>,
<0x218 &apps_smmu 0x1c06 0x0 0x1>,
<0x300 &apps_smmu 0x1c07 0x0 0x1>,
<0x400 &apps_smmu 0x1c08 0x0 0x1>,
<0x500 &apps_smmu 0x1c09 0x0 0x1>,
<0x501 &apps_smmu 0x1c10 0x0 0x1>;
status = "okay";
};
@ -151,22 +151,22 @@ pcie@0,1 {
};
&pcie1 {
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>,
<0x208 &apps_smmu 0x1c84 0x1>,
<0x210 &apps_smmu 0x1c85 0x1>,
<0x218 &apps_smmu 0x1c86 0x1>,
<0x300 &apps_smmu 0x1c87 0x1>,
<0x408 &apps_smmu 0x1c90 0x1>,
<0x410 &apps_smmu 0x1c91 0x1>,
<0x418 &apps_smmu 0x1c92 0x1>,
<0x500 &apps_smmu 0x1c93 0x1>,
<0x600 &apps_smmu 0x1c94 0x1>,
<0x700 &apps_smmu 0x1c95 0x1>,
<0x701 &apps_smmu 0x1c96 0x1>,
<0x800 &apps_smmu 0x1c97 0x1>,
<0x900 &apps_smmu 0x1c98 0x1>,
<0x901 &apps_smmu 0x1c99 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
<0x100 &apps_smmu 0x1c81 0x0 0x1>,
<0x208 &apps_smmu 0x1c84 0x0 0x1>,
<0x210 &apps_smmu 0x1c85 0x0 0x1>,
<0x218 &apps_smmu 0x1c86 0x0 0x1>,
<0x300 &apps_smmu 0x1c87 0x0 0x1>,
<0x408 &apps_smmu 0x1c90 0x0 0x1>,
<0x410 &apps_smmu 0x1c91 0x0 0x1>,
<0x418 &apps_smmu 0x1c92 0x0 0x1>,
<0x500 &apps_smmu 0x1c93 0x0 0x1>,
<0x600 &apps_smmu 0x1c94 0x0 0x1>,
<0x700 &apps_smmu 0x1c95 0x0 0x1>,
<0x701 &apps_smmu 0x1c96 0x0 0x1>,
<0x800 &apps_smmu 0x1c97 0x0 0x1>,
<0x900 &apps_smmu 0x1c98 0x0 0x1>,
<0x901 &apps_smmu 0x1c99 0x0 0x1>;
};
&pcie1_switch0_dsp1 {