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wifi: rtw89: 8851b: add TX power related functions
Get TX power value from tables according to selected country and channel, and set proper power to registers. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230519031500.21087-2-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
parent
8b21c08ef7
commit
76f2516f79
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@ -448,6 +448,34 @@ static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
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}
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}
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static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
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{
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#define __thm_setting(raw) \
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({ \
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u8 __v = (raw); \
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((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
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})
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struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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u8 i, val;
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if (!info->pg_thermal_trim) {
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[THERMAL][TRIM] no PG, do nothing\n");
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return;
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}
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for (i = 0; i < RF_PATH_NUM_8851B; i++) {
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val = __thm_setting(info->thermal_trim[i]);
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rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
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i, val);
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}
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#undef __thm_setting
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}
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static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
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u8 *phycap_map)
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{
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@ -468,6 +496,32 @@ static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
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}
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}
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static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
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{
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struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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u8 pabias_2g, pabias_5g;
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u8 i;
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if (!info->pg_pa_bias_trim) {
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[PA_BIAS][TRIM] no PG, do nothing\n");
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return;
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}
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for (i = 0; i < RF_PATH_NUM_8851B; i++) {
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pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0));
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pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4));
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
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i, pabias_2g, pabias_5g);
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rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
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rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
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}
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}
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static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
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{
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static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
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@ -565,6 +619,12 @@ static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
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}
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}
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static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
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{
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rtw8851b_thermal_trim(rtwdev);
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rtw8851b_pa_bias_trim(rtwdev);
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}
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static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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u8 mac_idx)
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@ -1355,6 +1415,195 @@ static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
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}
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}
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static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx, s16 ref)
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{
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const u16 tssi_16dbm_cw = 0x12c;
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const u8 base_cw_0db = 0x27;
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const s8 ofst_int = 0;
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s16 pwr_s10_3;
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s16 rf_pwr_cw;
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u16 bb_pwr_cw;
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u32 pwr_cw;
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u32 tssi_ofst_cw;
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pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
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bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));
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rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));
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rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
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pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
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tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
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rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
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"[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
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tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
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return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) |
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u32_encode_bits(pwr_cw, B_DPD_PWR_CW) |
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u32_encode_bits(ref, B_DPD_REF);
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}
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static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx)
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{
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static const u32 addr[RF_PATH_NUM_8851B] = {0x5800};
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const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
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const u8 ofst_ofdm = 0x4;
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const u8 ofst_cck = 0x8;
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const s16 ref_ofdm = 0;
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const s16 ref_cck = 0;
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u32 val;
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u8 i;
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rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
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rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
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B_AX_PWR_REF, 0x0);
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rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
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val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
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for (i = 0; i < RF_PATH_NUM_8851B; i++)
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rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
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phy_idx);
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rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
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val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
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for (i = 0; i < RF_PATH_NUM_8851B; i++)
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rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
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phy_idx);
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}
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static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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u8 tx_shape_idx,
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enum rtw89_phy_idx phy_idx)
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{
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#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
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#define __DFIR_CFG_MASK 0xffffffff
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#define __DFIR_CFG_NR 8
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#define __DECL_DFIR_PARAM(_name, _val...) \
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static const u32 param_ ## _name[] = {_val}; \
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static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
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__DECL_DFIR_PARAM(flat,
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0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
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0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
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__DECL_DFIR_PARAM(sharp,
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0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
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0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
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__DECL_DFIR_PARAM(sharp_14,
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0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
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0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
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u8 ch = chan->channel;
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const u32 *param;
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u32 addr;
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int i;
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if (ch > 14) {
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rtw89_warn(rtwdev,
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"set tx shape dfir by unknown ch: %d on 2G\n", ch);
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return;
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}
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if (ch == 14)
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param = param_sharp_14;
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else
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param = tx_shape_idx == 0 ? param_flat : param_sharp;
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for (i = 0; i < __DFIR_CFG_NR; i++) {
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addr = __DFIR_CFG_ADDR(i);
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rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
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"set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
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rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
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phy_idx);
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}
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#undef __DECL_DFIR_PARAM
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#undef __DFIR_CFG_NR
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#undef __DFIR_CFG_MASK
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#undef __DECL_CFG_ADDR
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}
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static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_phy_idx phy_idx)
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{
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u8 band = chan->band_type;
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u8 regd = rtw89_regd_get(rtwdev, band);
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u8 tx_shape_cck = rtw89_8851b_tx_shape[band][RTW89_RS_CCK][regd];
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u8 tx_shape_ofdm = rtw89_8851b_tx_shape[band][RTW89_RS_OFDM][regd];
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if (band == RTW89_BAND_2G)
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rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
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rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
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tx_shape_ofdm);
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}
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static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_phy_idx phy_idx)
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{
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rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
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rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
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rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
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rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
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rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
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}
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static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx)
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{
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rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
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}
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static
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void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
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s8 pw_ofst, enum rtw89_mac_idx mac_idx)
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{
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u32 reg;
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if (pw_ofst < -16 || pw_ofst > 15) {
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rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
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return;
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}
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reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx);
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rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
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reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
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rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
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pw_ofst = max_t(s8, pw_ofst - 3, -16);
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reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
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rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
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}
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static int
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rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
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{
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int ret;
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ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
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if (ret)
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return ret;
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ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
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if (ret)
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return ret;
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ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
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if (ret)
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return ret;
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rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
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RTW89_MAC_1 : RTW89_MAC_0);
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return 0;
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}
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static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
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{
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struct rtw89_btc *btc = &rtwdev->btc;
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@ -1711,6 +1960,11 @@ static const struct rtw89_chip_ops rtw8851b_chip_ops = {
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.read_phycap = rtw8851b_read_phycap,
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.fem_setup = NULL,
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.rfe_gpio = rtw8851b_rfe_gpio,
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.power_trim = rtw8851b_power_trim,
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.set_txpwr = rtw8851b_set_txpwr,
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.set_txpwr_ctrl = rtw8851b_set_txpwr_ctrl,
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.init_txpwr_unit = rtw8851b_init_txpwr_unit,
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.set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset,
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.pwr_on_func = rtw8851b_pwr_on_func,
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.pwr_off_func = rtw8851b_pwr_off_func,
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.fill_txdesc = rtw89_core_fill_txdesc,
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