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irqchip/renesas-rzv2h: Update TSSR_TIEN macro

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On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. Replace the
macro ICU_TSSR_TIEN(n)->ICU_TSSR_TIEN(n, _field_width) for supporting both
these SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/all/20250224131253.134199-11-biju.das.jz@bp.renesas.com
This commit is contained in:
Biju Das 2025-02-24 13:11:26 +00:00 committed by Thomas Gleixner
parent 1a6ebcc10b
commit 76c3b77473
1 changed files with 8 additions and 4 deletions
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12
drivers/irqchip/irq-renesas-rzv2h.c
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@ -66,7 +66,11 @@
#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8))
#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n)
#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8))
#define ICU_TSSR_TIEN(n, field_width) \
({\
typeof(field_width) (_field_width) = (field_width); \
BIT((_field_width) - 1) << ((n) * (_field_width)); \
})
#define ICU_TITSR_K(tint_nr) ((tint_nr) / 16)
#define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16)
@ -153,9 +157,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
guard(raw_spinlock)(&priv->lock);
tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
if (enable)
tssr |= ICU_TSSR_TIEN(tssel_n);
tssr |= ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
else
tssr &= ~ICU_TSSR_TIEN(tssel_n);
tssr &= ~ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
}
@ -314,7 +318,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
nr_tint = 32 / priv->info->field_width;
tssr_k = tint_nr / nr_tint;
tssel_n = tint_nr % nr_tint;
tien = ICU_TSSR_TIEN(tssel_n);
tien = ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
titsr_k = ICU_TITSR_K(tint_nr);
titsel_n = ICU_TITSR_TITSEL_N(tint_nr);