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drm/amd/display: Add FRL support to clk_mgr, dsc, hdcp

Browse Source 
This adds a few, relatively minor, changes for FRL to
clk_mgr, DSC, and HDCP blocks.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2026-04-24 12:22:18 -04:00 committed by Alex Deucher
parent d36771a034
commit 76a2db58e9
9 changed files with 62 additions and 0 deletions
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3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
View File

@ -93,6 +93,9 @@ static int dcn31_get_active_display_cnt_wa(
if (dc_is_dp_signal(stream->signal) && !stream->dpms_off)
display_count++;
/* FRL can't be tracked by DIG enablement */
if (dc_is_hdmi_frl_signal(stream->signal))
display_count++;
}
for (i = 0; i < dc->link_count; i++) {

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
View File

@ -127,6 +127,9 @@ static int dcn314_get_active_display_cnt_wa(
if (dc_is_dp_signal(stream->signal) && !stream->dpms_off)
display_count++;
/* FRL can't be tracked by DIG enablement */
if (dc_is_hdmi_frl_signal(stream->signal))
display_count++;
}
for (i = 0; i < dc->link_count; i++) {

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
View File

@ -69,6 +69,9 @@ static int dcn315_get_active_display_cnt_wa(
stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
tmds_present = true;
/* FRL can't be tracked by DIG enablement */
if (dc_is_hdmi_frl_signal(stream->signal))
display_count++;
}
for (i = 0; i < dc->link_count; i++) {

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
View File

@ -81,6 +81,9 @@ static int dcn316_get_active_display_cnt_wa(
stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
tmds_present = true;
/* FRL can't be tracked by DIG enablement */
if (dc_is_hdmi_frl_signal(stream->signal))
display_count++;
}
for (i = 0; i < dc->link_count; i++) {

12
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
View File

@ -283,6 +283,18 @@ static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||
dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
if (pipe_ctx->stream_res.audio != NULL)
dto_params.req_audio_dtbclk_khz = 24000;
}
if (dc_is_hdmi_signal(pipe_ctx->stream->signal) ||
dc_is_dvi_signal(pipe_ctx->stream->signal))
dto_params.is_hdmi = true;
dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
//dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
}

14
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
View File

@ -232,6 +232,8 @@ void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context
if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) {
has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&
dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);
has_active_hpo = has_active_hpo || (old_pipe->stream->signal == SIGNAL_TYPE_HDMI_FRL &&
new_pipe->stream->signal == SIGNAL_TYPE_HDMI_FRL);
}
@ -271,6 +273,18 @@ static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||
dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
if (pipe_ctx->stream_res.audio != NULL)
dto_params.req_audio_dtbclk_khz = 24000;
}
if (dc_is_hdmi_signal(pipe_ctx->stream->signal) ||
dc_is_dvi_signal(pipe_ctx->stream->signal))
dto_params.is_hdmi = true;
dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
//dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
}

18
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
View File

@ -542,6 +542,7 @@ static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr
ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);
use_hpo_encoder |= dc_is_hdmi_frl_signal(otg_master->stream->signal);
if (!use_hpo_encoder)
continue;
@ -1095,6 +1096,9 @@ static unsigned int dcn401_build_update_display_clocks_sequence(
bool update_dispclk = false;
bool update_dppclk = false;
bool dppclk_lowered = false;
struct pipe_ctx *otg_master;
bool frl_present = false;
unsigned int i;
unsigned int num_steps = 0;
@ -1127,6 +1131,20 @@ static unsigned int dcn401_build_update_display_clocks_sequence(
/* DCCG requires KHz precision for DTBCLK */
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
for (i = 0; i < context->stream_count; i++) {
otg_master = resource_get_otg_master_for_stream(
&context->res_ctx, context->streams[i]);
if (otg_master != NULL &&
otg_master->stream != NULL &&
dc_is_hdmi_frl_signal(otg_master->stream->signal)) {
frl_present = true;
break;
}
}
if (frl_present)
block_sequence[num_steps].params.update_hardmin_params.freq_mhz =
(uint16_t)clk_mgr_base->bw_params->clk_table.entries[
clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels - 1].dtbclk_mhz;
block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
num_steps++;

5
drivers/gpu/drm/amd/display/dc/dsc/dsc.h
View File

@ -102,6 +102,11 @@ struct dsc_enc_caps {
int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */
int32_t max_slice_width;
uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
bool is_frl;
bool is_vic_all_bpp;
uint32_t total_chunk_kbytes;
uint32_t num_lanes;
uint32_t frl_rate;
uint32_t edp_sink_max_bits_per_pixel;
bool is_dp;
};

1
drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
View File

@ -365,6 +365,7 @@ static const struct protection_properties *get_protection_properties_by_signal(
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
case SIGNAL_TYPE_HDMI_FRL:
return &hdmi_14_protection; //todo version2.2
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST: