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ARM: dts: qcom: msm8226: Add more SoC bits
Add nodes for sdhc, uart4, i2c, scm, smem, rpm-requests including dependencies. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> [bjorn: Moved other nodes before "soc" to keep things alphabetical] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210911232707.259615-5-luca@z3ntu.xyz
This commit is contained in:
Luca Weiss
Bjorn Andersson
parent
61339f368d
commit
7694892a93
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@ -7,6 +7,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8974.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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@ -20,6 +21,70 @@ memory@0 {
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reg = <0x0 0x0>;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-msm8226", "qcom,scm";
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clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
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clock-names = "core", "bus", "iface";
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};
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x80>;
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#hwlock-cells = <1>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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smem_region: smem@3000000 {
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reg = <0x3000000 0x100000>;
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no-map;
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};
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};
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smd {
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compatible = "qcom,smd";
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rpm {
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 0>;
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qcom,smd-edge = <15>;
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rpm_requests: rpm-requests {
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compatible = "qcom,rpm-msm8226";
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qcom,smd-channels = "rpm_requests";
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};
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -34,6 +99,136 @@ intc: interrupt-controller@f9000000 {
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#interrupt-cells = <3>;
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};
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apcs: syscon@f9011000 {
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compatible = "syscon";
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reg = <0xf9011000 0x1000>;
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};
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sdhc_1: sdhci@f9824900 {
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compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>,
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<&gcc GCC_SDCC1_AHB_CLK>,
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<&xo_board>;
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clock-names = "core", "iface", "xo";
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status = "disabled";
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};
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sdhc_2: sdhci@f98a4900 {
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compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_APPS_CLK>,
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<&gcc GCC_SDCC2_AHB_CLK>,
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<&xo_board>;
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clock-names = "core", "iface", "xo";
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status = "disabled";
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};
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sdhc_3: sdhci@f9864900 {
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compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC3_APPS_CLK>,
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<&gcc GCC_SDCC3_AHB_CLK>,
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<&xo_board>;
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clock-names = "core", "iface", "xo";
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status = "disabled";
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};
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blsp1_uart3: serial@f991f000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991f000 0x1000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_uart4: serial@f9920000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf9920000 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_i2c1: i2c@f9923000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9923000 0x1000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c1_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c2: i2c@f9924000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9924000 0x1000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c2_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c3: i2c@f9925000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9925000 0x1000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c3_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c4: i2c@f9926000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9926000 0x1000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c4_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c5: i2c@f9927000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9927000 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c5_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gcc: clock-controller@fc400000 {
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compatible = "qcom,gcc-msm8226";
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reg = <0xfc400000 0x4000>;
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@ -51,15 +246,41 @@ tlmm: pinctrl@fd510000 {
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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};
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blsp1_uart3: serial@f991f000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991f000 0x1000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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blsp1_i2c1_pins: blsp1-i2c1 {
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pins = "gpio2", "gpio3";
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function = "blsp_i2c1";
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drive-strength = <2>;
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bias-disable;
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};
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blsp1_i2c2_pins: blsp1-i2c2 {
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pins = "gpio6", "gpio7";
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function = "blsp_i2c2";
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drive-strength = <2>;
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bias-disable;
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};
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blsp1_i2c3_pins: blsp1-i2c3 {
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pins = "gpio10", "gpio11";
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function = "blsp_i2c3";
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drive-strength = <2>;
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bias-disable;
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};
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blsp1_i2c4_pins: blsp1-i2c4 {
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pins = "gpio14", "gpio15";
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function = "blsp_i2c4";
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drive-strength = <2>;
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bias-disable;
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};
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blsp1_i2c5_pins: blsp1-i2c5 {
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pins = "gpio18", "gpio19";
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function = "blsp_i2c5";
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drive-strength = <2>;
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bias-disable;
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};
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};
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restart@fc4ab000 {
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@ -67,6 +288,22 @@ restart@fc4ab000 {
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reg = <0xfc4ab000 0x4>;
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};
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spmi_bus: spmi@fc4cf000 {
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compatible = "qcom,spmi-pmic-arb";
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reg-names = "core", "intr", "cnfg";
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reg = <0xfc4cf000 0x1000>,
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<0xfc4cb000 0x1000>,
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<0xfc4ca000 0x1000>;
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interrupt-names = "periph_irq";
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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rng@f9bff000 {
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compatible = "qcom,prng";
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reg = <0xf9bff000 0x200>;
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@ -131,6 +368,16 @@ frame@f9028000 {
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status = "disabled";
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};
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};
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rpm_msg_ram: memory@fc428000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0xfc428000 0x4000>;
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};
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tcsr_mutex_block: syscon@fd484000 {
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compatible = "syscon";
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reg = <0xfd484000 0x2000>;
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};
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};
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timer {
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