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riscv: cmpxchg: Use .option arch for Zacas and Zabha

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Instead of adding these to -march globally, use .option arch to use
instructions from these extensions only in code paths where we know they
are available, like how it is done for most other extensions.
TOOLCHAIN_HAS_{ZACAS,ZABHA} already depend on AS_HAS_OPTION_ARCH, so
this is not a functionality regression even on older assemblers.

Although the compiler is unlikely to generate atomics on its own accord,
this aligns handling of Zacas and Zabha with most other extensions and
improves consistency on how assembly code requiring extra extensions is
written in kernel code.

This is analogous to the use of __LSE_PREAMBLE or .arch_extension lse in
arm64 code.

Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Reviewed-by: Jesse Taube <jtaubepe@redhat.com>
Link: https://patch.msgid.link/20260717-riscv-no-zacas-zabha-in-march-v1-1-82b5b0799fb6@iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Vivian Wang 2026-08-07 19:24:32 -06:00 committed by Paul Walmsley
parent 7e4cb63d61
commit 7655525298
2 changed files with 13 additions and 7 deletions
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6
arch/riscv/Makefile
View File

@ -75,12 +75,6 @@ else
riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
endif
# Check if the toolchain supports Zacas
riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas
# Check if the toolchain supports Zabha
riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha
KBUILD_BASE_ISA = -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
export KBUILD_BASE_ISA

14
arch/riscv/include/asm/cmpxchg.h
View File

@ -23,7 +23,10 @@
riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA)) { \
__asm__ __volatile__ ( \
prepend \
" .option push\n" \
" .option arch, +zabha\n" \
" amoswap" swap_sfx " %0, %z2, %1\n" \
" .option pop\n" \
swap_append \
: "=&r" (r), "+A" (*(p)) \
: "rJ" (n) \
@ -141,7 +144,10 @@
\
__asm__ __volatile__ ( \
cas_prepend \
" .option push\n" \
" .option arch, +zacas, +zabha\n" \
" amocas" cas_sfx " %0, %z2, %1\n" \
" .option pop\n" \
cas_append \
: "+&r" (r), "+A" (*(p)) \
: "rJ" (n) \
@ -188,7 +194,10 @@
\
__asm__ __volatile__ ( \
cas_prepend \
" .option push\n" \
" .option arch, +zacas\n" \
" amocas" cas_sfx " %0, %z2, %1\n" \
" .option pop\n" \
cas_append \
: "+&r" (r), "+A" (*(p)) \
: "rJ" (n) \
@ -340,7 +349,10 @@ union __u128_halves {
register unsigned long t4 asm ("t4") = __ho.high; \
\
__asm__ __volatile__ ( \
" amocas.q" cas_sfx " %0, %z3, %2" \
" .option push\n" \
" .option arch, +zacas\n" \
" amocas.q" cas_sfx " %0, %z3, %2\n" \
" .option pop\n" \
: "+&r" (t3), "+&r" (t4), "+A" (*(p)) \
: "rJ" (t1), "rJ" (t2) \
: "memory"); \