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Revert "parisc: Set PCI CLS early in boot."

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This reverts the following patch, which shouldn't have been applied
to the .32 stable tree as it causes problems.


  commit 5fd4514bb3 upstream.

  Set the PCI CLS early in the boot process to prevent
  device failures. In pcibios_set_master use the new
  pci_cache_line_size instead of a hard-coded value.

  Signed-off-by: Carlos O'Donell <carlos@codesourcery.com>
  Reviewed-by: Grant Grundler <grundler@google.com>
  Signed-off-by: Kyle McMartin <kyle@redhat.com>
  Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>


Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Greg Kroah-Hartman 2010-05-24 14:58:13 -07:00
parent 0ddd11675c
commit 763f2ee657
1 changed files with 2 additions and 5 deletions
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7
arch/parisc/kernel/pci.c
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@ -18,6 +18,7 @@
#include <asm/io.h>
#include <asm/system.h>
#include <asm/cache.h> /* for L1_CACHE_BYTES */
#include <asm/superio.h>
#define DEBUG_RESOURCES 0
@ -122,10 +123,6 @@ static int __init pcibios_init(void)
} else {
printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
}
/* Set the CLS for PCI as early as possible. */
pci_cache_line_size = pci_dfl_cache_line_size;
return 0;
}
@ -174,7 +171,7 @@ void pcibios_set_master(struct pci_dev *dev)
** upper byte is PCI_LATENCY_TIMER.
*/
pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
(0x80 << 8) | pci_cache_line_size);
(0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
}