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drm/i915/display: Split out DG2 MPLLB enable helper
Refactor the DG2 MPLLB enable path by splitting out a helper that programs the PHY directly from an intel_mpllb_state. This is preparatory work for moving DG2 MPLLB handling under the DPLL framework, where callbacks operate on dpll_hw_state rather than the full crtc_state. Assisted-by: Copilot:claude-sonnet-4-6 Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/20260630115336.1059976-2-mika.kahola@intel.com
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@ -1816,11 +1816,10 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
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return -EINVAL;
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}
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void intel_mpllb_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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void intel_mpllb_enable_phy(struct intel_encoder *encoder,
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const struct intel_mpllb_state *pll_state)
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{
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struct intel_display *display = to_intel_display(encoder);
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const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;
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enum phy phy = intel_encoder_to_phy(encoder);
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intel_reg_t enable_reg = (phy <= PHY_D ?
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DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
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@ -1875,6 +1874,12 @@ void intel_mpllb_enable(struct intel_encoder *encoder,
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*/
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}
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void intel_mpllb_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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intel_mpllb_enable_phy(encoder, &crtc_state->dpll_hw_state.mpllb);
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}
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void intel_mpllb_disable(struct intel_encoder *encoder)
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{
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struct intel_display *display = to_intel_display(encoder);
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@ -22,6 +22,8 @@ void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,
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int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder);
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void intel_mpllb_enable_phy(struct intel_encoder *encoder,
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const struct intel_mpllb_state *pll_state);
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void intel_mpllb_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_mpllb_disable(struct intel_encoder *encoder);
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