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Renesas RZ/G3E Pin Control DT Binding Definitions
Pin control DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and DT source files. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZ3hDOwAKCRCKwlD9ZEnx cO0MAQDIZaN9Ry+BBi8nksGT2tQtnSEXni2iqZzaKfN1CrBe4AEAuFup2hkQhhLy MD2fvxNTacoXxgy7iGy764SORPlccgs= =vf2c -----END PGP SIGNATURE----- Merge tag 'renesas-r9a09g047-dt-binding-defs-tag2' into renesas-pinctrl-for-v6.14 Renesas RZ/G3E Pin Control DT Binding Definitions Pin control DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and DT source files.
This commit is contained in:
Geert Uytterhoeven
commit
75ea9cf9b8
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@ -4,19 +4,22 @@
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$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
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title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
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and control of clock signals for the IP modules, generation and control of resets,
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and control over booting, low power consumption and power supply domains.
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On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
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generation and control of clock signals for the IP modules, generation and
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control of resets, and control over booting, low power consumption and power
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supply domains.
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properties:
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compatible:
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const: renesas,r9a09g057-cpg
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enum:
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- renesas,r9a09g047-cpg # RZ/G3E
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- renesas,r9a09g057-cpg # RZ/V2H
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reg:
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maxItems: 1
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@ -37,7 +40,7 @@ properties:
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
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<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number. The module number is calculated as the CLKON register
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offset index multiplied by 16, plus the actual bit in the register
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@ -26,6 +26,7 @@ properties:
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- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
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- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
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- renesas,r9a08g045-pinctrl # RZ/G3S
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- renesas,r9a09g047-pinctrl # RZ/G3E
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- renesas,r9a09g057-pinctrl # RZ/V2H(P)
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- items:
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@ -125,7 +126,7 @@ additionalProperties:
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drive-push-pull: true
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renesas,output-impedance:
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description:
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Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
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Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
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property corresponds to register bit values that can be set in the PFC_IOLH_mn
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register, which adjusts the drive strength value and is pin-dependent.
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$ref: /schemas/types.yaml#/definitions/uint32
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@ -142,7 +143,9 @@ allOf:
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properties:
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compatible:
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contains:
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const: renesas,r9a09g057-pinctrl
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enum:
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- renesas,r9a09g047-pinctrl
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- renesas,r9a09g057-pinctrl
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then:
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properties:
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resets:
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@ -525,6 +525,23 @@ properties:
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- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
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- const: renesas,r9a09g011
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- description: RZ/G3E (R9A09G047)
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items:
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- enum:
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- renesas,smarc2-evk # RZ SMARC Carrier-II EVK
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- enum:
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- renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
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- enum:
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- renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
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- renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
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- renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
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- renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
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- renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
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- renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
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- renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
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- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
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- const: renesas,r9a09g047
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- description: RZ/V2H(P) (R9A09G057)
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items:
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- enum:
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21
include/dt-bindings/clock/renesas,r9a09g047-cpg.h
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include/dt-bindings/clock/renesas,r9a09g047-cpg.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
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#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* Core Clock list */
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#define R9A09G047_SYS_0_PCLK 0
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#define R9A09G047_CA55_0_CORECLK0 1
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#define R9A09G047_CA55_0_CORECLK1 2
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#define R9A09G047_CA55_0_CORECLK2 3
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#define R9A09G047_CA55_0_CORECLK3 4
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#define R9A09G047_CA55_0_PERIPHCLK 5
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#define R9A09G047_CM33_CLK0 6
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#define R9A09G047_CST_0_SWCLKTCK 7
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#define R9A09G047_IOTOP_0_SHCLK 8
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
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41
include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
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41
include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* This header provides constants for Renesas RZ/G3E family pinctrl bindings.
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*
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*/
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#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
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#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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/* RZG3E_Px = Offset address of PFC_P_mn - 0x20 */
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#define RZG3E_P0 0
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#define RZG3E_P1 1
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#define RZG3E_P2 2
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#define RZG3E_P3 3
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#define RZG3E_P4 4
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#define RZG3E_P5 5
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#define RZG3E_P6 6
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#define RZG3E_P7 7
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#define RZG3E_P8 8
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#define RZG3E_PA 10
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#define RZG3E_PB 11
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#define RZG3E_PC 12
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#define RZG3E_PD 13
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#define RZG3E_PE 14
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#define RZG3E_PF 15
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#define RZG3E_PG 16
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#define RZG3E_PH 17
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#define RZG3E_PJ 19
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#define RZG3E_PK 20
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#define RZG3E_PL 21
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#define RZG3E_PM 22
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#define RZG3E_PS 28
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#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
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#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin)
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#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */
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