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soc: mediatek: mtk-dvfsrc: Add support for DVFSRCv4 and MT8196
Add support for the DVFSRC Version 4 by adding new functions for vcore/dram levels (in v4, called gears instead), and for readout of pre-programmed dvfsrc_opp entries, corresponding to each gear. In the probe function, for v4, the curr_opps is initialized from the get_hw_opps() function instead of platform data. In order to make use of the new DVFSRCv4 code, also add support for the MediaTek MT8196 SoC. Co-developed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
AngeloGioacchino Del Regno
parent
7cf9db2aca
commit
75cf308fee
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@ -15,11 +15,17 @@
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#include <linux/soc/mediatek/dvfsrc.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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/* DVFSRC_BASIC_CONTROL */
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#define DVFSRC_V4_BASIC_CTRL_OPP_COUNT GENMASK(26, 20)
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/* DVFSRC_LEVEL */
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#define DVFSRC_V1_LEVEL_TARGET_LEVEL GENMASK(15, 0)
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#define DVFSRC_TGT_LEVEL_IDLE 0x00
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#define DVFSRC_V1_LEVEL_CURRENT_LEVEL GENMASK(31, 16)
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#define DVFSRC_V4_LEVEL_TARGET_LEVEL GENMASK(15, 8)
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#define DVFSRC_V4_LEVEL_TARGET_PRESENT BIT(16)
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/* DVFSRC_SW_REQ, DVFSRC_SW_REQ2 */
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#define DVFSRC_V1_SW_REQ2_DRAM_LEVEL GENMASK(1, 0)
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#define DVFSRC_V1_SW_REQ2_VCORE_LEVEL GENMASK(3, 2)
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@ -27,9 +33,23 @@
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#define DVFSRC_V2_SW_REQ_DRAM_LEVEL GENMASK(3, 0)
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#define DVFSRC_V2_SW_REQ_VCORE_LEVEL GENMASK(6, 4)
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#define DVFSRC_V4_SW_REQ_EMI_LEVEL GENMASK(3, 0)
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#define DVFSRC_V4_SW_REQ_DRAM_LEVEL GENMASK(15, 12)
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/* DVFSRC_VCORE */
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#define DVFSRC_V2_VCORE_REQ_VSCP_LEVEL GENMASK(14, 12)
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/* DVFSRC_TARGET_GEAR */
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#define DVFSRC_V4_GEAR_TARGET_DRAM GENMASK(7, 0)
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#define DVFSRC_V4_GEAR_TARGET_VCORE GENMASK(15, 8)
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/* DVFSRC_GEAR_INFO */
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#define DVFSRC_V4_GEAR_INFO_REG_WIDTH 0x4
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#define DVFSRC_V4_GEAR_INFO_REG_LEVELS 64
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#define DVFSRC_V4_GEAR_INFO_VCORE GENMASK(3, 0)
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#define DVFSRC_V4_GEAR_INFO_EMI GENMASK(7, 4)
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#define DVFSRC_V4_GEAR_INFO_DRAM GENMASK(15, 12)
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#define DVFSRC_POLL_TIMEOUT_US 1000
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#define STARTUP_TIME_US 1
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@ -52,6 +72,7 @@ struct dvfsrc_bw_constraints {
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struct dvfsrc_opp {
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u32 vcore_opp;
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u32 dram_opp;
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u32 emi_opp;
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};
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struct dvfsrc_opp_desc {
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@ -72,6 +93,7 @@ struct mtk_dvfsrc {
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struct dvfsrc_soc_data {
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const int *regs;
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const u8 *bw_units;
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const bool has_emi_ddr;
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const struct dvfsrc_opp_desc *opps_desc;
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u32 (*calc_dram_bw)(struct mtk_dvfsrc *dvfsrc, int type, u64 bw);
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@ -79,6 +101,8 @@ struct dvfsrc_soc_data {
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u32 (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
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u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
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u32 (*get_vscp_level)(struct mtk_dvfsrc *dvfsrc);
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u32 (*get_opp_count)(struct mtk_dvfsrc *dvfsrc);
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int (*get_hw_opps)(struct mtk_dvfsrc *dvfsrc);
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void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
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void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
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void (*set_dram_hrt_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
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@ -101,6 +125,7 @@ static void dvfsrc_writel(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
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}
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enum dvfsrc_regs {
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DVFSRC_BASIC_CONTROL,
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DVFSRC_SW_REQ,
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DVFSRC_SW_REQ2,
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DVFSRC_LEVEL,
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@ -110,6 +135,9 @@ enum dvfsrc_regs {
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DVFSRC_SW_HRT_BW,
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DVFSRC_SW_EMI_BW,
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DVFSRC_VCORE,
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DVFSRC_TARGET_GEAR,
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DVFSRC_GEAR_INFO_L,
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DVFSRC_GEAR_INFO_H,
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DVFSRC_REGS_MAX,
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};
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@ -130,6 +158,22 @@ static const int dvfsrc_mt8195_regs[] = {
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[DVFSRC_TARGET_LEVEL] = 0xd48,
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};
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static const int dvfsrc_mt8196_regs[] = {
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[DVFSRC_BASIC_CONTROL] = 0x0,
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[DVFSRC_SW_REQ] = 0x18,
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[DVFSRC_VCORE] = 0x80,
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[DVFSRC_GEAR_INFO_L] = 0xfc,
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[DVFSRC_SW_BW] = 0x1e8,
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[DVFSRC_SW_PEAK_BW] = 0x1f4,
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[DVFSRC_SW_HRT_BW] = 0x20c,
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[DVFSRC_LEVEL] = 0x5f0,
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[DVFSRC_TARGET_LEVEL] = 0x5f0,
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[DVFSRC_SW_REQ2] = 0x604,
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[DVFSRC_SW_EMI_BW] = 0x60c,
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[DVFSRC_TARGET_GEAR] = 0x6ac,
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[DVFSRC_GEAR_INFO_H] = 0x6b0,
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};
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static const struct dvfsrc_opp *dvfsrc_get_current_opp(struct mtk_dvfsrc *dvfsrc)
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{
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u32 level = dvfsrc->dvd->get_current_level(dvfsrc);
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@ -137,6 +181,20 @@ static const struct dvfsrc_opp *dvfsrc_get_current_opp(struct mtk_dvfsrc *dvfsrc
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return &dvfsrc->curr_opps->opps[level];
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}
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static u32 dvfsrc_get_current_target_vcore_gear(struct mtk_dvfsrc *dvfsrc)
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{
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u32 val = dvfsrc_readl(dvfsrc, DVFSRC_TARGET_GEAR);
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return FIELD_GET(DVFSRC_V4_GEAR_TARGET_VCORE, val);
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}
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static u32 dvfsrc_get_current_target_dram_gear(struct mtk_dvfsrc *dvfsrc)
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{
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u32 val = dvfsrc_readl(dvfsrc, DVFSRC_TARGET_GEAR);
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return FIELD_GET(DVFSRC_V4_GEAR_TARGET_DRAM, val);
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}
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static bool dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc)
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{
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if (!dvfsrc->dvd->get_target_level)
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@ -193,6 +251,24 @@ static int dvfsrc_wait_for_opp_level_v2(struct mtk_dvfsrc *dvfsrc, u32 level)
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return 0;
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}
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static int dvfsrc_wait_for_vcore_level_v4(struct mtk_dvfsrc *dvfsrc, u32 level)
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{
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u32 val;
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return readx_poll_timeout_atomic(dvfsrc_get_current_target_vcore_gear,
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dvfsrc, val, val >= level,
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STARTUP_TIME_US, DVFSRC_POLL_TIMEOUT_US);
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}
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static int dvfsrc_wait_for_opp_level_v4(struct mtk_dvfsrc *dvfsrc, u32 level)
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{
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u32 val;
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return readx_poll_timeout_atomic(dvfsrc_get_current_target_dram_gear,
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dvfsrc, val, val >= level,
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STARTUP_TIME_US, DVFSRC_POLL_TIMEOUT_US);
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}
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static u32 dvfsrc_get_target_level_v1(struct mtk_dvfsrc *dvfsrc)
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{
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u32 val = dvfsrc_readl(dvfsrc, DVFSRC_LEVEL);
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@ -226,6 +302,27 @@ static u32 dvfsrc_get_current_level_v2(struct mtk_dvfsrc *dvfsrc)
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return 0;
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}
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static u32 dvfsrc_get_target_level_v4(struct mtk_dvfsrc *dvfsrc)
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{
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u32 val = dvfsrc_readl(dvfsrc, DVFSRC_TARGET_LEVEL);
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if (val & DVFSRC_V4_LEVEL_TARGET_PRESENT)
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return FIELD_GET(DVFSRC_V4_LEVEL_TARGET_LEVEL, val) + 1;
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return 0;
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}
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static u32 dvfsrc_get_current_level_v4(struct mtk_dvfsrc *dvfsrc)
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{
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u32 level = dvfsrc_readl(dvfsrc, DVFSRC_LEVEL) + 1;
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/* Valid levels */
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if (level < dvfsrc->curr_opps->num_opp)
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return dvfsrc->curr_opps->num_opp - level;
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/* Zero for level 0 or invalid level */
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return 0;
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}
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static u32 dvfsrc_get_vcore_level_v1(struct mtk_dvfsrc *dvfsrc)
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{
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u32 val = dvfsrc_readl(dvfsrc, DVFSRC_SW_REQ2);
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@ -277,11 +374,30 @@ static void dvfsrc_set_vscp_level_v2(struct mtk_dvfsrc *dvfsrc, u32 level)
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dvfsrc_writel(dvfsrc, DVFSRC_VCORE, val);
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}
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static u32 dvfsrc_get_opp_count_v4(struct mtk_dvfsrc *dvfsrc)
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{
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u32 val = dvfsrc_readl(dvfsrc, DVFSRC_BASIC_CONTROL);
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return FIELD_GET(DVFSRC_V4_BASIC_CTRL_OPP_COUNT, val) + 1;
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}
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static u32 dvfsrc_calc_dram_bw_v1(struct mtk_dvfsrc *dvfsrc, int type, u64 bw)
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{
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return (u32)div_u64(bw, 100 * 1000);
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}
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static u32 dvfsrc_calc_dram_bw_v4(struct mtk_dvfsrc *dvfsrc, int type, u64 bw)
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{
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u8 bw_unit = dvfsrc->dvd->bw_units[type];
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u64 bw_mbps;
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if (type < DVFSRC_BW_AVG || type >= DVFSRC_BW_MAX)
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return 0;
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bw_mbps = div_u64(bw, 1000);
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return (u32)div_u64((bw_mbps + bw_unit - 1), bw_unit);
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}
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static void __dvfsrc_set_dram_bw_v1(struct mtk_dvfsrc *dvfsrc, u32 reg,
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int type, u16 max_bw, u16 min_bw, u64 bw)
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{
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@ -333,6 +449,100 @@ static void dvfsrc_set_opp_level_v1(struct mtk_dvfsrc *dvfsrc, u32 level)
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dvfsrc_writel(dvfsrc, DVFSRC_SW_REQ, val);
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}
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static u32 dvfsrc_get_opp_gear(struct mtk_dvfsrc *dvfsrc, u8 level)
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{
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u32 reg_ofst, val;
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u8 idx;
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/* Calculate register offset and index for requested gear */
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if (level < DVFSRC_V4_GEAR_INFO_REG_LEVELS) {
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reg_ofst = dvfsrc->dvd->regs[DVFSRC_GEAR_INFO_L];
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idx = level;
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} else {
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reg_ofst = dvfsrc->dvd->regs[DVFSRC_GEAR_INFO_H];
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idx = level - DVFSRC_V4_GEAR_INFO_REG_LEVELS;
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}
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reg_ofst += DVFSRC_V4_GEAR_INFO_REG_WIDTH * (level / 2);
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/* Read the corresponding gear register */
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val = readl(dvfsrc->regs + reg_ofst);
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/* Each register contains two sets of data, 16 bits per gear */
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val >>= 16 * (idx % 2);
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return val;
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}
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static int dvfsrc_get_hw_opps_v4(struct mtk_dvfsrc *dvfsrc)
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{
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struct dvfsrc_opp *dvfsrc_opps;
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struct dvfsrc_opp_desc *desc;
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u32 num_opps, gear_info;
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u8 num_vcore, num_dram;
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u8 num_emi;
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int i;
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num_opps = dvfsrc_get_opp_count_v4(dvfsrc);
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if (num_opps == 0) {
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dev_err(dvfsrc->dev, "No OPPs programmed in DVFSRC MCU.\n");
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return -EINVAL;
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}
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/*
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* The first 16 bits set in the gear info table says how many OPPs
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* and how many vcore, dram and emi table entries are available.
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*/
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gear_info = dvfsrc_readl(dvfsrc, DVFSRC_GEAR_INFO_L);
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if (gear_info == 0) {
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dev_err(dvfsrc->dev, "No gear info in DVFSRC MCU.\n");
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return -EINVAL;
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}
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num_vcore = FIELD_GET(DVFSRC_V4_GEAR_INFO_VCORE, gear_info) + 1;
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num_dram = FIELD_GET(DVFSRC_V4_GEAR_INFO_DRAM, gear_info) + 1;
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num_emi = FIELD_GET(DVFSRC_V4_GEAR_INFO_EMI, gear_info) + 1;
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dev_info(dvfsrc->dev,
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"Discovered %u gears and %u vcore, %u dram, %u emi table entries.\n",
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num_opps, num_vcore, num_dram, num_emi);
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/* Allocate everything now as anything else after that cannot fail */
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desc = devm_kzalloc(dvfsrc->dev, sizeof(*desc), GFP_KERNEL);
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if (!desc)
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return -ENOMEM;
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dvfsrc_opps = devm_kcalloc(dvfsrc->dev, num_opps + 1,
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sizeof(*dvfsrc_opps), GFP_KERNEL);
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if (!dvfsrc_opps)
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return -ENOMEM;
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/* Read the OPP table gear indices */
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for (i = 0; i <= num_opps; i++) {
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gear_info = dvfsrc_get_opp_gear(dvfsrc, num_opps - i);
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dvfsrc_opps[i].vcore_opp = FIELD_GET(DVFSRC_V4_GEAR_INFO_VCORE, gear_info);
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dvfsrc_opps[i].dram_opp = FIELD_GET(DVFSRC_V4_GEAR_INFO_DRAM, gear_info);
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dvfsrc_opps[i].emi_opp = FIELD_GET(DVFSRC_V4_GEAR_INFO_EMI, gear_info);
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};
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desc->num_opp = num_opps + 1;
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desc->opps = dvfsrc_opps;
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/* Assign to main structure now that everything is done! */
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dvfsrc->curr_opps = desc;
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return 0;
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}
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static void dvfsrc_set_dram_level_v4(struct mtk_dvfsrc *dvfsrc, u32 level)
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{
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u32 val = dvfsrc_readl(dvfsrc, DVFSRC_SW_REQ);
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val &= ~DVFSRC_V4_SW_REQ_DRAM_LEVEL;
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val |= FIELD_PREP(DVFSRC_V4_SW_REQ_DRAM_LEVEL, level);
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dev_dbg(dvfsrc->dev, "%s level=%u\n", __func__, level);
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dvfsrc_writel(dvfsrc, DVFSRC_SW_REQ, val);
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}
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int mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data)
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{
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struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev);
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@ -448,7 +658,14 @@ static int mtk_dvfsrc_probe(struct platform_device *pdev)
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dvfsrc->dram_type = ares.a1;
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dev_dbg(&pdev->dev, "DRAM Type: %d\n", dvfsrc->dram_type);
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dvfsrc->curr_opps = &dvfsrc->dvd->opps_desc[dvfsrc->dram_type];
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/* Newer versions of the DVFSRC MCU have pre-programmed gear tables */
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if (dvfsrc->dvd->get_hw_opps) {
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ret = dvfsrc->dvd->get_hw_opps(dvfsrc);
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if (ret)
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return ret;
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} else {
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dvfsrc->curr_opps = &dvfsrc->dvd->opps_desc[dvfsrc->dram_type];
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}
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platform_set_drvdata(pdev, dvfsrc);
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ret = devm_of_platform_populate(&pdev->dev);
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@ -576,10 +793,39 @@ static const struct dvfsrc_soc_data mt8195_data = {
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.bw_constraints = &dvfsrc_bw_constr_v2,
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};
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static const u8 mt8196_bw_units[] = {
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[DVFSRC_BW_AVG] = 64,
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[DVFSRC_BW_PEAK] = 64,
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[DVFSRC_BW_HRT] = 30,
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};
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static const struct dvfsrc_soc_data mt8196_data = {
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.regs = dvfsrc_mt8196_regs,
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.bw_units = mt8196_bw_units,
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.has_emi_ddr = true,
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.get_target_level = dvfsrc_get_target_level_v4,
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.get_current_level = dvfsrc_get_current_level_v4,
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.get_vcore_level = dvfsrc_get_vcore_level_v2,
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.get_vscp_level = dvfsrc_get_vscp_level_v2,
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.get_opp_count = dvfsrc_get_opp_count_v4,
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.get_hw_opps = dvfsrc_get_hw_opps_v4,
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.calc_dram_bw = dvfsrc_calc_dram_bw_v4,
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.set_dram_bw = dvfsrc_set_dram_bw_v1,
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.set_dram_peak_bw = dvfsrc_set_dram_peak_bw_v1,
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.set_dram_hrt_bw = dvfsrc_set_dram_hrt_bw_v1,
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.set_opp_level = dvfsrc_set_dram_level_v4,
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.set_vcore_level = dvfsrc_set_vcore_level_v2,
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.set_vscp_level = dvfsrc_set_vscp_level_v2,
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.wait_for_opp_level = dvfsrc_wait_for_opp_level_v4,
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.wait_for_vcore_level = dvfsrc_wait_for_vcore_level_v4,
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.bw_constraints = &dvfsrc_bw_constr_v1,
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};
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static const struct of_device_id mtk_dvfsrc_of_match[] = {
|
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{ .compatible = "mediatek,mt6893-dvfsrc", .data = &mt6893_data },
|
||||
{ .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_data },
|
||||
{ .compatible = "mediatek,mt8195-dvfsrc", .data = &mt8195_data },
|
||||
{ .compatible = "mediatek,mt8196-dvfsrc", .data = &mt8196_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user