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https://github.com/torvalds/linux.git
synced 2026-06-01 19:13:47 +02:00
Qualcomm Arm32 DeviceTree updates for v6.16
Introduce support for the AP8064-based LG Nexus 4. MSM8226 is extended with modem-related features, the LTE-capable variant MSM8926 is introduced, and modem support is enabled on Samsung Galaxy Tab 4. Display-related clocks and power-domains are defined for the simple framebuffer of Motorola Moto G, to allow booting without clk_ignore_unused and pd_ignore_unused. On MSM8960 SDCC BAM and thermal sensor (tsens) is introduced. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmgju+QVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FH7oQAMuLGyWTReLqQ3FCdnlI/kXWH2qF Fg4VJb2zM0eYpaBPXS8fkD0BlxXPHy/CD9A/yKWpHMkD706J4PlsCfMLzj6pzbJJ tzP9fA/v2deGl/G/OKsM+Yp7a6Ocl2VzXU2eOakWMBlWQUcTv020jz+4wNwKDwx3 85BESrpr6yCG55dOddZI1etKb2oVXKuvZAvYSELNb4l2PkIN+stJ0HoMykTWn9XD WD7QvD1LONi8eldt65O2Dz7cwN5eHybD4QPpYvW41OudP6reqTyTlE/NQSdP4eg5 RyKXevjYemZTGX5YsNFR2p/y3zhLU95LH8+MSIm0d7DlpLMPNz88hedCEM+Mr+fp egHAfH+smWNki5xlaWUZwbRCIKZVz6SR5utnzudcC9obJMOrtajvBjaQ1WbsrzS3 l4nka/Csn9KY/E0X6wKHXGzJlSOe87XlnF7HUlsfbzs1AQpNADgCtwFM5eJZLhhb TcxbjKh1ZOrznuPxCRA0na0zuH/kEgdchs4F4dsJ3/I42tDAXFYBmjw97R07J/Xx fJEtqhfvxTQSv5RR6cfbbayXPEJpvJ6uygmJCOx+ZzhRWroOqB7dlWp1/kForhAn FZYdu/4rZn9IWOJJEc0QcRLKyeekFca4pXMZfLk3nN6iGu7IwlWtzFr0wbgkVDBk m18POm/F0EA1BeG8 =kQf8 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmguSekACgkQmmx57+YA GNkaQxAAs+kfGjBKytJDybAG4Eh6EJ0UrMAMyPLqNx/DaXxM+QZ+ZLzFvMdNMz8i srLipwPQKyqN2EvYB0vWzx/3uAabVG8ZhIFYFFVVIpsy9jZkWF27Yw7ybAQg935P U+X5M26AdZv/Dkf1LYRcDZnSObtRL/Q8Hl+MxWjnt0GQDAtOX1DA3oksNvmdS7pQ pJEM0KX/PShZibpj0iGugGMMTBwvwHlj2hLpNrBCjISuHXwhbufXs6bEyoXcV5SL FuS8aK3eOvr2PntZsrHArJxRZMXKPBA17F2NsifCnucmt0Lqmz8V92lObGiORkHr kTvrJmIc1CSwSZrFyhq1C+azs2rx++BvCl7mFElK1tn9czod7LT7wUasDRu185wY qGGtg1dvfotxAI1ctt3ogtKu4pBONwbnb5cNjxPTHy0pNPIOBiCWy4NGxM3wJ7wJ zKukpczNwk7H1NFAd+0sx0XnGebGhz3Qs9jV3VD7sjdYdMZlIBYce13Rl9j70nWV OKcMjW0NYC+SNa/1vNE4ZpUqKjIiOvVXi9MPKnR2DPKKXXO1B8lT4pMcgr06wysL 60fqIcqghsoeQEAwc20geimkgJkxusbpAXNqX9eY/kZOy7s2eVdzoXPLeCt0FEWV x2jNix94bPZLujFKb9jhpYZl4dz6/6RK/yYZwm+x4klJKxO+Z/c= =2aVB -----END PGP SIGNATURE----- Merge tag 'qcom-arm32-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm32 DeviceTree updates for v6.16 Introduce support for the AP8064-based LG Nexus 4. MSM8226 is extended with modem-related features, the LTE-capable variant MSM8926 is introduced, and modem support is enabled on Samsung Galaxy Tab 4. Display-related clocks and power-domains are defined for the simple framebuffer of Motorola Moto G, to allow booting without clk_ignore_unused and pd_ignore_unused. On MSM8960 SDCC BAM and thermal sensor (tsens) is introduced. * tag 'qcom-arm32-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: ARM: dts: qcom: apq8064: move replicator out of soc node ARM: dts: qcom: apq8064: use new compatible for SPS SIC device ARM: dts: qcom: apq8064: use new compatible for SFPB device ARM: dts: qcom: apq8064 merge hw splinlock into corresponding syscon device ARM: dts: qcom: apq8064: add missing clocks to the timer node ARM: dts: qcom: apq8064-lg-nexus4-mako: Enable WiFi ARM: dts: qcom: msm8226-motorola-falcon: specify vddio_disp output voltage ARM: dts: qcom: msm8226-motorola-falcon: limit TPS65132 to 5.4V ARM: dts: qcom: msm8226-motorola-falcon: add I2C clock frequencies ARM: dts: qcom: msm8226-motorola-falcon: add clocks, power-domain to simpleFB ARM: dts: qcom: ipq4019: Drop redundant CPU "clock-latency" ARM: dts: qcom: sdx55/sdx65: Fix CPU power-domain-names ARM: dts: qcom: msm8974: Use the header with DSI phy clock IDs ARM: dts: qcom: msm8226: Use the header with DSI phy clock IDs Link: https://lore.kernel.org/r/20250513214111.43401-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
759dd3fea1
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@ -31,6 +31,15 @@ framebuffer@3200000 {
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vsp-supply = <®_lcd_pos>;
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vsn-supply = <®_lcd_neg>;
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vddio-supply = <&vddio_disp_vreg>;
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clocks = <&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_AXI_CLK>,
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<&mmcc MDSS_BYTE0_CLK>,
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<&mmcc MDSS_ESC0_CLK>,
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<&mmcc MDSS_MDP_CLK>,
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<&mmcc MMSS_MISC_AHB_CLK>,
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<&mmcc MDSS_PCLK0_CLK>,
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<&mmcc MDSS_VSYNC_CLK>;
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power-domains = <&mmcc MDSS_GDSC>;
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};
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};
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@ -53,9 +62,12 @@ key-volume-up {
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};
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};
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/* TI TPS22902 */
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vddio_disp_vreg: regulator-vddio-disp {
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compatible = "regulator-fixed";
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regulator-name = "vddio_disp";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>;
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vin-supply = <&pm8226_l8>;
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startup-delay-us = <300>;
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@ -97,6 +109,7 @@ reserved@fb00000 {
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};
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&blsp1_i2c2 {
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clock-frequency = <100000>;
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status = "okay";
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magnetometer@c {
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@ -126,6 +139,7 @@ accelerometer@19 {
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};
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&blsp1_i2c3 {
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clock-frequency = <400000>;
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status = "okay";
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regulator@3e {
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@ -136,8 +150,8 @@ regulator@3e {
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reg_lcd_pos: outp {
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regulator-name = "outp";
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regulator-min-microvolt = <4000000>;
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regulator-max-microvolt = <6000000>;
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regulator-min-microvolt = <5400000>;
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regulator-max-microvolt = <5400000>;
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regulator-active-discharge = <1>;
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regulator-boot-on;
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enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
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@ -145,8 +159,8 @@ reg_lcd_pos: outp {
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reg_lcd_neg: outn {
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regulator-name = "outn";
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regulator-min-microvolt = <4000000>;
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regulator-max-microvolt = <6000000>;
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regulator-min-microvolt = <5400000>;
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regulator-max-microvolt = <5400000>;
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regulator-active-discharge = <1>;
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regulator-boot-on;
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enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>;
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@ -86,6 +86,24 @@ MATRIX_KEY(0, 1, KEY_VOLUMEUP)
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status = "okay";
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};
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&riva {
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pinctrl-names = "default";
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pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
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vddcx-supply = <&pm8921_s3>;
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vddmx-supply = <&pm8921_l24>;
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vddpx-supply = <&pm8921_s4>;
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status = "okay";
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iris {
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vddxo-supply = <&pm8921_l4>;
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vddrfa-supply = <&pm8921_s2>;
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vddpa-supply = <&pm8921_l10>;
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vdddig-supply = <&pm8921_lvs2>;
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};
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};
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&rpm {
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regulators {
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compatible = "qcom,rpm-pm8921-regulators";
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@ -213,12 +213,6 @@ sleep_clk: sleep_clk {
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};
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};
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sfpb_mutex: hwmutex {
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compatible = "qcom,sfpb-mutex";
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syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
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#hwlock-cells = <1>;
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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@ -284,6 +278,40 @@ scm {
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};
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};
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replicator {
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compatible = "arm,coresight-static-replicator";
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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replicator_in: endpoint {
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remote-endpoint = <&funnel_out>;
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};
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};
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};
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator_out0: endpoint {
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remote-endpoint = <&etb_in>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out1: endpoint {
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remote-endpoint = <&tpiu_in>;
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};
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};
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -305,9 +333,10 @@ tlmm_pinmux: pinctrl@800000 {
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pinctrl-0 = <&ps_hold_default_state>;
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};
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sfpb_wrapper_mutex: syscon@1200000 {
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compatible = "syscon";
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reg = <0x01200000 0x8000>;
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sfpb_mutex: hwmutex@1200600 {
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compatible = "qcom,sfpb-mutex";
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reg = <0x01200600 0x100>;
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#hwlock-cells = <1>;
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};
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intc: interrupt-controller@2000000 {
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@ -326,6 +355,8 @@ timer@200a000 {
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <27000000>;
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clocks = <&sleep_clk>;
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clock-names = "sleep";
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cpu-offset = <0x80000>;
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};
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@ -405,8 +436,8 @@ saw3_vreg: regulator {
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};
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};
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sps_sic_non_secure: sps-sic-non-secure@12100000 {
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compatible = "syscon";
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sps_sic_non_secure: interrupt-controller@12100000 {
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compatible = "qcom,apq8064-sps-sic", "syscon";
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reg = <0x12100000 0x10000>;
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};
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@ -1089,7 +1120,7 @@ opp-27000000 {
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};
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mmss_sfpb: syscon@5700000 {
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compatible = "syscon";
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compatible = "qcom,apq8064-mmss-sfpb", "syscon";
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reg = <0x5700000 0x70>;
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};
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@ -1532,39 +1563,6 @@ tpiu_in: endpoint {
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};
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};
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replicator {
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compatible = "arm,coresight-static-replicator";
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator_out0: endpoint {
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remote-endpoint = <&etb_in>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out1: endpoint {
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remote-endpoint = <&tpiu_in>;
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};
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};
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};
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in-ports {
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port {
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replicator_in: endpoint {
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remote-endpoint = <&funnel_out>;
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};
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};
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};
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};
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funnel@1a04000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x1a04000 0x1000>;
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@ -53,7 +53,6 @@ cpu@0 {
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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@ -67,7 +66,6 @@ cpu@1 {
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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@ -81,7 +79,6 @@ cpu@2 {
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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@ -95,7 +92,6 @@ cpu@3 {
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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@ -6,6 +6,7 @@
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <dt-bindings/clock/qcom,gcc-msm8974.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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@ -1138,8 +1139,8 @@ mmcc: clock-controller@fd8c0000 {
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<&gcc GPLL0_VOTE>,
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<&gcc GPLL1_VOTE>,
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<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
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<&mdss_dsi0_phy 1>,
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<&mdss_dsi0_phy 0>;
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<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
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<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>;
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clock-names = "xo",
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"mmss_gpll0_vote",
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"gpll0_vote",
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@ -1215,8 +1216,8 @@ mdss_dsi0: dsi@fd922800 {
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assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
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<&mmcc PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi0_phy 0>,
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<&mdss_dsi0_phy 1>;
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assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
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<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
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clocks = <&mmcc MDSS_MDP_CLK>,
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<&mmcc MDSS_AHB_CLK>,
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@ -3,6 +3,7 @@
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#include <dt-bindings/interconnect/qcom,msm8974.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <dt-bindings/clock/qcom,gcc-msm8974.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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@ -1871,10 +1872,10 @@ mmcc: clock-controller@fd8c0000 {
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<&gcc GPLL0_VOTE>,
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<&gcc GPLL1_VOTE>,
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<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
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<&mdss_dsi0_phy 1>,
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<&mdss_dsi0_phy 0>,
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<&mdss_dsi1_phy 1>,
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<&mdss_dsi1_phy 0>,
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<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
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<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
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<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
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<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
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<0>,
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<0>,
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<0>;
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@ -1961,8 +1962,10 @@ mdss_dsi0: dsi@fd922800 {
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
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assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
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<&mmcc PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
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<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
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clocks = <&mmcc MDSS_MDP_CLK>,
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<&mmcc MDSS_AHB_CLK>,
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@ -2032,8 +2035,10 @@ mdss_dsi1: dsi@fd922e00 {
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
|
||||
assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
|
||||
<&mmcc PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
|
||||
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
|
||||
|
||||
clocks = <&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_AHB_CLK>,
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ cpu0: cpu@0 {
|
|||
enable-method = "psci";
|
||||
clocks = <&apcs>;
|
||||
power-domains = <&rpmhpd SDX55_CX>;
|
||||
power-domain-names = "rpmhpd";
|
||||
power-domain-names = "perf";
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ cpu0: cpu@0 {
|
|||
enable-method = "psci";
|
||||
clocks = <&apcs>;
|
||||
power-domains = <&rpmhpd SDX65_CX_AO>;
|
||||
power-domain-names = "rpmhpd";
|
||||
power-domain-names = "perf";
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user