github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-03 12:03:54 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

ath11k: add hw reg support for WCN6855

Browse Source 
Reg address of WCN6855 is different from other devices,
so add separate reg definition for this target.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1

Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Baochen Qiang <bqiang@codeaurora.org>
Signed-off-by: Jouni Malinen <jouni@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20210511162214.29475-2-jouni@codeaurora.org
This commit is contained in:
Baochen Qiang 2021-05-31 17:41:27 +03:00 committed by Kalle Valo
parent fb312ac5cc
commit 755b1f7317
2 changed files with 72 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
drivers/net/wireless/ath/ath11k/hw.c
View File

@ -1688,3 +1688,74 @@ const struct ath11k_hw_regs qcn9074_regs = {
.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
};
const struct ath11k_hw_regs wcn6855_regs = {
/* SW2TCL(x) R0 ring configuration address */
.hal_tcl1_ring_base_lsb = 0x00000690,
.hal_tcl1_ring_base_msb = 0x00000694,
.hal_tcl1_ring_id = 0x00000698,
.hal_tcl1_ring_misc = 0x000006a0,
.hal_tcl1_ring_tp_addr_lsb = 0x000006ac,
.hal_tcl1_ring_tp_addr_msb = 0x000006b0,
.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0,
.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4,
.hal_tcl1_ring_msi1_base_lsb = 0x000006d8,
.hal_tcl1_ring_msi1_base_msb = 0x000006dc,
.hal_tcl1_ring_msi1_data = 0x000006e0,
.hal_tcl2_ring_base_lsb = 0x000006e8,
.hal_tcl_ring_base_lsb = 0x00000798,
/* TCL STATUS ring address */
.hal_tcl_status_ring_base_lsb = 0x000008a0,
/* REO2SW(x) R0 ring configuration address */
.hal_reo1_ring_base_lsb = 0x00000244,
.hal_reo1_ring_base_msb = 0x00000248,
.hal_reo1_ring_id = 0x0000024c,
.hal_reo1_ring_misc = 0x00000254,
.hal_reo1_ring_hp_addr_lsb = 0x00000258,
.hal_reo1_ring_hp_addr_msb = 0x0000025c,
.hal_reo1_ring_producer_int_setup = 0x00000268,
.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
.hal_reo1_ring_msi1_base_msb = 0x00000290,
.hal_reo1_ring_msi1_data = 0x00000294,
.hal_reo2_ring_base_lsb = 0x0000029c,
.hal_reo1_aging_thresh_ix_0 = 0x000005bc,
.hal_reo1_aging_thresh_ix_1 = 0x000005c0,
.hal_reo1_aging_thresh_ix_2 = 0x000005c4,
.hal_reo1_aging_thresh_ix_3 = 0x000005c8,
/* REO2SW(x) R2 ring pointers (head/tail) address */
.hal_reo1_ring_hp = 0x00003030,
.hal_reo1_ring_tp = 0x00003034,
.hal_reo2_ring_hp = 0x00003038,
/* REO2TCL R0 ring configuration address */
.hal_reo_tcl_ring_base_lsb = 0x00000454,
.hal_reo_tcl_ring_hp = 0x00003060,
/* REO status address */
.hal_reo_status_ring_base_lsb = 0x0000055c,
.hal_reo_status_hp = 0x00003078,
/* WCSS relative address */
.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
.hal_seq_wcss_umac_ce1_src_reg = 0x1b82000,
.hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000,
/* WBM Idle address */
.hal_wbm_idle_link_ring_base_lsb = 0x00000870,
.hal_wbm_idle_link_ring_misc = 0x00000880,
/* SW2WBM release address */
.hal_wbm_release_ring_base_lsb = 0x000001e8,
/* WBM2SW release address */
.hal_wbm0_release_ring_base_lsb = 0x00000920,
.hal_wbm1_release_ring_base_lsb = 0x00000978,
/* PCIe base address */
.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
};

1
drivers/net/wireless/ath/ath11k/hw.h
View File

@ -318,5 +318,6 @@ struct ath11k_hw_regs {
extern const struct ath11k_hw_regs ipq8074_regs;
extern const struct ath11k_hw_regs qca6390_regs;
extern const struct ath11k_hw_regs qcn9074_regs;
extern const struct ath11k_hw_regs wcn6855_regs;
#endif