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iommu/vt-d: Add pasid replace helpers
pasid replacement allows converting a present pasid entry to be FS, SS, PT or nested, hence add helpers for such operations. Suggested-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Yi Liu <yi.l.liu@intel.com> Link: https://lore.kernel.org/r/20241107122234.7424-5-yi.l.liu@intel.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Yi Liu
Joerg Roedel
parent
2cb5ff623d
commit
7543ee63e8
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@ -389,6 +389,50 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
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return 0;
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}
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int intel_pasid_replace_first_level(struct intel_iommu *iommu,
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struct device *dev, pgd_t *pgd,
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u32 pasid, u16 did, u16 old_did,
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int flags)
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{
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struct pasid_entry *pte, new_pte;
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if (!ecap_flts(iommu->ecap)) {
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pr_err("No first level translation support on %s\n",
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iommu->name);
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return -EINVAL;
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}
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if ((flags & PASID_FLAG_FL5LP) && !cap_fl5lp_support(iommu->cap)) {
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pr_err("No 5-level paging support for first-level on %s\n",
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iommu->name);
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return -EINVAL;
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}
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pasid_pte_config_first_level(iommu, &new_pte, pgd, did, flags);
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spin_lock(&iommu->lock);
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pte = intel_pasid_get_entry(dev, pasid);
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if (!pte) {
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spin_unlock(&iommu->lock);
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return -ENODEV;
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}
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if (!pasid_pte_is_present(pte)) {
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spin_unlock(&iommu->lock);
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return -EINVAL;
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}
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WARN_ON(old_did != pasid_get_domain_id(pte));
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*pte = new_pte;
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spin_unlock(&iommu->lock);
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intel_pasid_flush_present(iommu, dev, pasid, old_did, pte);
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intel_iommu_drain_pasid_prq(dev, pasid);
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return 0;
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}
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/*
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* Set up the scalable mode pasid entry for second only translation type.
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*/
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@ -456,6 +500,57 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu,
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return 0;
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}
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int intel_pasid_replace_second_level(struct intel_iommu *iommu,
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struct dmar_domain *domain,
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struct device *dev, u16 old_did,
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u32 pasid)
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{
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struct pasid_entry *pte, new_pte;
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struct dma_pte *pgd;
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u64 pgd_val;
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u16 did;
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/*
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* If hardware advertises no support for second level
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* translation, return directly.
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*/
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if (!ecap_slts(iommu->ecap)) {
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pr_err("No second level translation support on %s\n",
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iommu->name);
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return -EINVAL;
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}
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pgd = domain->pgd;
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pgd_val = virt_to_phys(pgd);
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did = domain_id_iommu(domain, iommu);
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pasid_pte_config_second_level(iommu, &new_pte, pgd_val,
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domain->agaw, did,
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domain->dirty_tracking);
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spin_lock(&iommu->lock);
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pte = intel_pasid_get_entry(dev, pasid);
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if (!pte) {
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spin_unlock(&iommu->lock);
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return -ENODEV;
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}
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if (!pasid_pte_is_present(pte)) {
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spin_unlock(&iommu->lock);
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return -EINVAL;
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}
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WARN_ON(old_did != pasid_get_domain_id(pte));
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*pte = new_pte;
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spin_unlock(&iommu->lock);
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intel_pasid_flush_present(iommu, dev, pasid, old_did, pte);
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intel_iommu_drain_pasid_prq(dev, pasid);
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return 0;
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}
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/*
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* Set up dirty tracking on a second only or nested translation type.
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*/
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@ -568,6 +663,38 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
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return 0;
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}
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int intel_pasid_replace_pass_through(struct intel_iommu *iommu,
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struct device *dev, u16 old_did,
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u32 pasid)
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{
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struct pasid_entry *pte, new_pte;
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u16 did = FLPT_DEFAULT_DID;
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pasid_pte_config_pass_through(iommu, &new_pte, did);
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spin_lock(&iommu->lock);
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pte = intel_pasid_get_entry(dev, pasid);
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if (!pte) {
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spin_unlock(&iommu->lock);
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return -ENODEV;
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}
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if (!pasid_pte_is_present(pte)) {
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spin_unlock(&iommu->lock);
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return -EINVAL;
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}
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WARN_ON(old_did != pasid_get_domain_id(pte));
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*pte = new_pte;
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spin_unlock(&iommu->lock);
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intel_pasid_flush_present(iommu, dev, pasid, old_did, pte);
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intel_iommu_drain_pasid_prq(dev, pasid);
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return 0;
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}
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/*
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* Set the page snoop control for a pasid entry which has been set up.
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*/
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@ -698,6 +825,69 @@ int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev,
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return 0;
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}
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int intel_pasid_replace_nested(struct intel_iommu *iommu,
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struct device *dev, u32 pasid,
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u16 old_did, struct dmar_domain *domain)
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{
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struct iommu_hwpt_vtd_s1 *s1_cfg = &domain->s1_cfg;
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struct dmar_domain *s2_domain = domain->s2_domain;
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u16 did = domain_id_iommu(domain, iommu);
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struct pasid_entry *pte, new_pte;
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/* Address width should match the address width supported by hardware */
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switch (s1_cfg->addr_width) {
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case ADDR_WIDTH_4LEVEL:
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break;
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case ADDR_WIDTH_5LEVEL:
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if (!cap_fl5lp_support(iommu->cap)) {
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dev_err_ratelimited(dev,
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"5-level paging not supported\n");
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return -EINVAL;
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}
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break;
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default:
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dev_err_ratelimited(dev, "Invalid stage-1 address width %d\n",
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s1_cfg->addr_width);
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return -EINVAL;
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}
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if ((s1_cfg->flags & IOMMU_VTD_S1_SRE) && !ecap_srs(iommu->ecap)) {
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pr_err_ratelimited("No supervisor request support on %s\n",
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iommu->name);
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return -EINVAL;
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}
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if ((s1_cfg->flags & IOMMU_VTD_S1_EAFE) && !ecap_eafs(iommu->ecap)) {
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pr_err_ratelimited("No extended access flag support on %s\n",
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iommu->name);
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return -EINVAL;
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}
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pasid_pte_config_nestd(iommu, &new_pte, s1_cfg, s2_domain, did);
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spin_lock(&iommu->lock);
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pte = intel_pasid_get_entry(dev, pasid);
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if (!pte) {
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spin_unlock(&iommu->lock);
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return -ENODEV;
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}
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if (!pasid_pte_is_present(pte)) {
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spin_unlock(&iommu->lock);
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return -EINVAL;
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}
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WARN_ON(old_did != pasid_get_domain_id(pte));
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*pte = new_pte;
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spin_unlock(&iommu->lock);
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intel_pasid_flush_present(iommu, dev, pasid, old_did, pte);
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intel_iommu_drain_pasid_prq(dev, pasid);
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return 0;
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}
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/*
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* Interfaces to setup or teardown a pasid table to the scalable-mode
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* context table entry:
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@ -303,6 +303,21 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
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struct device *dev, u32 pasid);
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int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev,
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u32 pasid, struct dmar_domain *domain);
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int intel_pasid_replace_first_level(struct intel_iommu *iommu,
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struct device *dev, pgd_t *pgd,
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u32 pasid, u16 did, u16 old_did,
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int flags);
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int intel_pasid_replace_second_level(struct intel_iommu *iommu,
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struct dmar_domain *domain,
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struct device *dev, u16 old_did,
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u32 pasid);
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int intel_pasid_replace_pass_through(struct intel_iommu *iommu,
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struct device *dev, u16 old_did,
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u32 pasid);
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int intel_pasid_replace_nested(struct intel_iommu *iommu,
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struct device *dev, u32 pasid,
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u16 old_did, struct dmar_domain *domain);
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void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
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struct device *dev, u32 pasid,
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bool fault_ignore);
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