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drm/msm/dpu: Add handling of LM_6 and LM_7 bits in pending flush mask

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MDSS/MDP v12 comes with new bits in flush registers (e.g.
MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/651260/
Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-13-8cab30c3e4df@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Krzysztof Kozlowski 2025-04-30 15:00:43 +02:00 committed by Dmitry Baryshkov
parent a5539d0fbb
commit 7520803bb9
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
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@ -261,6 +261,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(struct dpu_hw_ctl *ctx,
case LM_5:
ctx->pending_flush_mask |= BIT(20);
break;
case LM_6:
ctx->pending_flush_mask |= BIT(21);
break;
case LM_7:
ctx->pending_flush_mask |= BIT(27);
break;
default:
break;
}