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mtd: spi-nor: winbond: Add W25H02NWxxAM CMP locking support

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This chip has support for the locking complement (CMP) feature. Add
the relevant bit to enable it.

Unfortunately, this chip also comes with an incorrect BFPT table,
indicating the Control Register cannot be read back. This is wrong,
reading back the register works and has no (observed) side effect. The
datasheet clearly indicates supporting the 35h command and all bits from
the CR are marked readable. QE and CMP bits are inside, and can be
properly read back.

Add a fixup for this, otherwise it would defeat the use of the CMP
feature.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
This commit is contained in:
Miquel Raynal 2026-05-26 16:56:49 +02:00 committed by Pratyush Yadav
parent 855599425e
commit 751e4b02c4
1 changed files with 23 additions and 1 deletions
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24
drivers/mtd/spi-nor/winbond.c
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@ -73,6 +73,26 @@ static const struct spi_nor_fixups w25q256_fixups = {
.post_bfpt = w25q256_post_bfpt_fixups,
};
static int
winbond_rdcr_post_bfpt_fixup(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt)
{
/*
* W25H02NW, unlike its W25H512NW nor W25H01NW cousins, improperly sets
* the QE BFPT configuration bits, indicating a non readable CR. This is
* both incorrect and impractical, as the chip features a CMP bit for its
* locking scheme that lays in the Control Register, and needs to be read.
*/
nor->flags &= ~SNOR_F_NO_READ_CR;
return 0;
}
static const struct spi_nor_fixups winbond_rdcr_fixup = {
.post_bfpt = winbond_rdcr_post_bfpt_fixup,
};
/**
* winbond_nor_select_die() - Set active die.
* @nor: pointer to 'struct spi_nor'.
@ -370,7 +390,9 @@ static const struct flash_info winbond_nor_parts[] = {
}, {
/* W25H02NWxxAM */
.id = SNOR_ID(0xef, 0xa0, 0x22),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
.fixups = &winbond_rdcr_fixup,
},
};