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mailbox: qcom-cpucp: read mbox hardware register using readq()

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Mailbox hardware registers are 64 bit wide, but the interrupt handler
currently reads only 32 bits with readl() at offset 0x4 (upper 32
bits). This returns an incorrect value, while reading using readq()
returns the expected value.

Use readq() to access the 64 bit register and pass the expected value
to the mailbox client.

Fixes: 0e2a9a0310 ("mailbox: Add support for QTI CPUCP mailbox controller")
Signed-off-by: Sivansh Gupta <sivansh.gupta@oss.qualcomm.com>
Reviewed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
This commit is contained in:
Sivansh Gupta 2026-09-28 10:59:39 +05:30 committed by Jassi Brar
parent 134ef0278d
commit 74f1cf02d9
1 changed files with 1 additions and 1 deletions
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2
drivers/mailbox/qcom-cpucp-mbox.c
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@ -61,7 +61,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data)
status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) {
u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF);
u64 val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i));
struct mbox_chan *chan = &cpucp->chans[i];
struct mbox_client *cl;
unsigned long flags;