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perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields

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Support sampling of OPMASK registers via the sample_simd_pred_reg_*
fields.

Each OPMASK register consists of 1 u64 word. Current x86 hardware
supports 8 OPMASK registers. The perf_simd_reg_value() function is
responsible for outputting OPMASK value to userspace.

Additionally, sample_simd_pred_reg_qwords should be set to 1 to indicate
OPMASK sampling.

OPMASK sampling will be enabled in a subsequent patch that sets
PERF_PMU_CAP_SIMD_REGS.

Co-developed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260824082731.1013973-17-dapeng1.mi@linux.intel.com
This commit is contained in:
Dapeng Mi 2026-08-24 16:27:24 +08:00 committed by Peter Zijlstra
parent 3807f6996a
commit 74d55a827e
5 changed files with 66 additions and 7 deletions
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13
arch/x86/events/core.c
View File

@ -642,10 +642,11 @@ static int pebs_simd_regs_validate(struct perf_event *event)
if (event_needs_xmm(event) &&
x86_pmu.arch_pebs && !(caps & ARCH_PEBS_VECR_XMM))
return -EINVAL;
/* PEBS does not support YMM/ZMM registers sampling yet. */
/* PEBS does not support YMM/ZMM/OPMASK registers sampling yet. */
if (event_needs_ymm(event) ||
event_needs_low16_zmm(event) ||
event_needs_high16_zmm(event))
event_needs_high16_zmm(event) ||
event_needs_opmask(event))
return -EINVAL;
return 0;
@ -670,6 +671,9 @@ static int event_simd_regs_validate(struct perf_event *event)
if (event_needs_high16_zmm(event) &&
!(x86_pmu.ext_regs_mask & XFEATURE_MASK_Hi16_ZMM))
return -EINVAL;
if (event_needs_opmask(event) &&
!(x86_pmu.ext_regs_mask & XFEATURE_MASK_OPMASK))
return -EINVAL;
return 0;
}
@ -1836,6 +1840,7 @@ void x86_pmu_clear_perf_regs(struct pt_regs *regs)
perf_regs->ymmh_regs = NULL;
perf_regs->zmmh_regs = NULL;
perf_regs->h16zmm_regs = NULL;
perf_regs->opmask_regs = NULL;
}
static void update_perf_regs(struct x86_perf_regs *perf_regs,
@ -1857,6 +1862,8 @@ static void update_perf_regs(struct x86_perf_regs *perf_regs,
perf_regs->zmmh = get_xsave_addr(xsave, XFEATURE_ZMM_Hi256);
if (mask & XFEATURE_MASK_Hi16_ZMM)
perf_regs->h16zmm = get_xsave_addr(xsave, XFEATURE_Hi16_ZMM);
if (mask & XFEATURE_MASK_OPMASK)
perf_regs->opmask = get_xsave_addr(xsave, XFEATURE_OPMASK);
}
/*
@ -2031,6 +2038,8 @@ static u64 get_simd_sample_mask(struct perf_event *event, u64 sample_type)
mask |= XFEATURE_MASK_ZMM_Hi256;
if (__event_needs_high16_zmm(event, sample_type))
mask |= XFEATURE_MASK_Hi16_ZMM;
if (__event_needs_opmask(event, sample_type))
mask |= XFEATURE_MASK_OPMASK;
return mask;
}

27
arch/x86/events/perf_event.h
View File

@ -263,6 +263,33 @@ static inline bool event_needs_high16_zmm(struct perf_event *event)
PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
}
static inline bool __event_needs_opmask(struct perf_event *event,
u64 sample_type)
{
if (!event->attr.sample_simd_regs_enabled)
return false;
if (event->attr.sample_simd_pred_reg_qwords != PERF_X86_OPMASK_QWORDS)
return false;
if ((sample_type & PERF_SAMPLE_REGS_USER) &&
(event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
(event->attr.sample_simd_pred_reg_user > 0))
return true;
if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
(event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
(event->attr.sample_simd_pred_reg_intr > 0))
return true;
return false;
}
static inline bool event_needs_opmask(struct perf_event *event)
{
return __event_needs_opmask(event,
PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
}
struct amd_nb {
int nb_id; /* NorthBridge id */
int refcnt; /* reference count */

4
arch/x86/include/asm/perf_event.h
View File

@ -745,6 +745,10 @@ struct x86_perf_regs {
u64 *h16zmm_regs;
struct avx_512_hi16_state *h16zmm;
};
union {
u64 *opmask_regs;
struct avx_512_opmask_state *opmask;
};
};
extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);

5
arch/x86/include/uapi/asm/perf_regs.h
View File

@ -62,14 +62,19 @@ enum {
PERF_X86_SIMD_YMM_REGS = 16,
PERF_X86_SIMD_ZMM_REGS = 32,
PERF_X86_SIMD_VEC_REGS_MAX = PERF_X86_SIMD_ZMM_REGS,
PERF_X86_SIMD_OPMASK_REGS = 8,
PERF_X86_SIMD_PRED_REGS_MAX = PERF_X86_SIMD_OPMASK_REGS,
};
#define PERF_X86_SIMD_PRED_MASK __GENMASK(PERF_X86_SIMD_PRED_REGS_MAX - 1, 0)
#define PERF_X86_SIMD_VEC_MASK __GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0)
#define PERF_X86_H16ZMM_BASE 16
enum {
/* 1 qword = 8 bytes */
PERF_X86_OPMASK_QWORDS = 1,
PERF_X86_XMM_QWORDS = 2,
PERF_X86_YMM_QWORDS = 4,
PERF_X86_ZMM_QWORDS = 8,

24
arch/x86/kernel/perf_regs.c
View File

@ -89,8 +89,14 @@ u64 perf_simd_reg_value(struct pt_regs *regs, int idx,
if (!(perf_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD))
return 0;
if (pred)
return 0;
if (pred) {
if (WARN_ON_ONCE(idx >= PERF_X86_SIMD_PRED_REGS_MAX ||
qwords_idx >= PERF_X86_OPMASK_QWORDS))
return 0;
if (!perf_regs->opmask_regs)
return 0;
return perf_regs->opmask_regs[idx];
}
if (WARN_ON_ONCE(idx >= PERF_X86_SIMD_VEC_REGS_MAX ||
qwords_idx >= PERF_X86_SIMD_QWORDS_MAX))
@ -154,9 +160,17 @@ int perf_simd_reg_validate(u16 vec_qwords, u64 vec_mask,
return -EINVAL;
}
/* PRED registers are not supported yet. */
if (pred_qwords)
return -EINVAL;
if (pred_qwords) {
if (pred_qwords != PERF_X86_OPMASK_QWORDS)
return -EINVAL;
if (pred_mask & ~PERF_X86_SIMD_PRED_MASK)
return -EINVAL;
/* Only full-register sampling is allowed. */
mask = pred_mask;
if (pred_qwords == PERF_X86_OPMASK_QWORDS && mask &&
!bitmap_full(&mask, PERF_X86_SIMD_OPMASK_REGS))
return -EINVAL;
}
size = sizeof(u64) * 4;
size += (hweight64(vec_mask) * vec_qwords +