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ASoC: rockchip: spdif: Reorder clock enable sequence

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Enable the 'hclk' bus clock before the 'mclk' controller clock during
runtime resume.
The bus clock provides the register access interface, so enable it before
the controller clock. This also makes the resume sequence the reverse of
the suspend sequence, which keeps the clock ordering consistent.

Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
Link: https://patch.msgid.link/20260602101608.45137-3-phucduc.bui@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
bui duc phuc 2026-06-02 17:16:05 +07:00 committed by Mark Brown
parent d057cbc218
commit 74d3f01a90
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1 changed files with 5 additions and 5 deletions
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10
sound/soc/rockchip/rockchip_spdif.c
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@ -76,16 +76,16 @@ static int rk_spdif_runtime_resume(struct device *dev)
struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(spdif->mclk);
ret = clk_prepare_enable(spdif->hclk);
if (ret) {
dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
return ret;
}
ret = clk_prepare_enable(spdif->hclk);
ret = clk_prepare_enable(spdif->mclk);
if (ret) {
clk_disable_unprepare(spdif->mclk);
dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
clk_disable_unprepare(spdif->hclk);
dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
return ret;
}