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arm64: dts: qcom: sdm630: correct QFPROM byte offsets

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The NVMEM bindings expect that 'bits' property holds offset and size of
region within a byte, so it applies a constraint of <0, 7> for the
offset.  Using 25 as HSTX trim offset is within 4-byte QFPROM word, but
outside of the byte:

  sdm630-sony-xperia-nile-discovery.dtb: qfprom@780000: hstx-trim@240:bits:0:0: 25 is greater than the maximum of 7
  sdm630-sony-xperia-nile-discovery.dtb: qfprom@780000: gpu-speed-bin@41a0:bits:0:0: 21 is greater than the maximum of 7

Align the offsets to match the bindings.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220505113802.243301-6-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski 2022-05-05 13:38:02 +02:00 committed by Bjorn Andersson
parent b2eab35be1
commit 74b0fbd604
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/qcom/sdm630.dtsi
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@ -559,13 +559,13 @@ qfprom: qfprom@780000 {
#size-cells = <1>;
qusb2_hstx_trim: hstx-trim@240 {
reg = <0x240 0x1>;
bits = <25 3>;
reg = <0x243 0x1>;
bits = <1 3>;
};
gpu_speed_bin: gpu-speed-bin@41a0 {
reg = <0x41a0 0x1>;
bits = <21 7>;
reg = <0x41a2 0x1>;
bits = <5 7>;
};
};