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media: chips-media: wave5: separate irq setup routine

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Implement a separate setup routine for interrupts to reduce code
duplication. Also enable interrupts based on vpu_attr->support_encoders
and vpu_attr->support_decoders fields to facilitate support for other
Wave5xx IPs, because not all of them are both encoders and decoders.

Signed-off-by: Ivan Bornyakov <brnkv.i1@gmail.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
This commit is contained in:
Ivan Bornyakov 2024-04-15 13:07:21 +03:00 committed by Hans Verkuil
parent 2b9188426b
commit 749476d44d
1 changed files with 24 additions and 29 deletions
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53
drivers/media/platform/chips-media/wave5/wave5-hw.c
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@ -299,6 +299,27 @@ static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *ins
return wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL);
}
static void setup_wave5_interrupts(struct vpu_device *vpu_dev)
{
u32 reg_val = 0;
if (vpu_dev->attr.support_encoders) {
/* Encoder interrupt */
reg_val |= BIT(INT_WAVE5_ENC_SET_PARAM);
reg_val |= BIT(INT_WAVE5_ENC_PIC);
reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
}
if (vpu_dev->attr.support_decoders) {
/* Decoder interrupt */
reg_val |= BIT(INT_WAVE5_INIT_SEQ);
reg_val |= BIT(INT_WAVE5_DEC_PIC);
reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
}
return vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
}
static int setup_wave5_properties(struct device *dev)
{
struct vpu_device *vpu_dev = dev_get_drvdata(dev);
@ -340,6 +361,8 @@ static int setup_wave5_properties(struct device *dev)
p_attr->support_vcpu_backbone = FIELD_GET(FEATURE_VCPU_BACKBONE, hw_config_def0);
p_attr->support_vcore_backbone = FIELD_GET(FEATURE_VCORE_BACKBONE, hw_config_def0);
setup_wave5_interrupts(vpu_dev);
return 0;
}
@ -417,16 +440,6 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size)
wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
/* Encoder interrupt */
reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);
reg_val |= BIT(INT_WAVE5_ENC_PIC);
reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
/* Decoder interrupt */
reg_val |= BIT(INT_WAVE5_INIT_SEQ);
reg_val |= BIT(INT_WAVE5_DEC_PIC);
reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {
reg_val = ((WAVE5_PROC_AXI_ID << 28) |
@ -1034,16 +1047,6 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size)
wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
/* Encoder interrupt */
reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);
reg_val |= BIT(INT_WAVE5_ENC_PIC);
reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
/* Decoder interrupt */
reg_val |= BIT(INT_WAVE5_INIT_SEQ);
reg_val |= BIT(INT_WAVE5_DEC_PIC);
reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {
reg_val = ((WAVE5_PROC_AXI_ID << 28) |
@ -1134,15 +1137,7 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin
wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
/* Encoder interrupt */
reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);
reg_val |= BIT(INT_WAVE5_ENC_PIC);
reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
/* Decoder interrupt */
reg_val |= BIT(INT_WAVE5_INIT_SEQ);
reg_val |= BIT(INT_WAVE5_DEC_PIC);
reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
setup_wave5_interrupts(vpu_dev);
reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {